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70V24L25G PDF预览

70V24L25G

更新时间: 2024-11-28 10:36:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
25页 211K
描述
PGA-84, Tray

70V24L25G 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:PGA
包装说明:1.120 X 1.120 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-84针数:84
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.72
最长访问时间:25 ns其他特性:INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O 类型:COMMONJESD-30 代码:S-CPGA-P84
JESD-609代码:e0长度:27.94 mm
内存密度:65536 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16湿度敏感等级:1
功能数量:1端口数量:2
端子数量:84字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX16输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA84M,11X11封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:5.207 mm
最大待机电流:0.0025 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.165 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:27.94 mm
Base Number Matches:1

70V24L25G 数据手册

 浏览型号70V24L25G的Datasheet PDF文件第2页浏览型号70V24L25G的Datasheet PDF文件第3页浏览型号70V24L25G的Datasheet PDF文件第4页浏览型号70V24L25G的Datasheet PDF文件第5页浏览型号70V24L25G的Datasheet PDF文件第6页浏览型号70V24L25G的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
8/4K x 18 DUAL-PORT  
8/4K x 16 DUAL-PORT  
STATIC RAM  
IDT70V35/34S/L  
IDT70V25/24S/L  
Features  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
IDT70V35/34 (IDT70V25/24) easily expands data bus width  
to 36 bits (32 bits) or more using the Master/Slave select  
when cascading more than one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
BUSY and Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in a 100-pin TQFP (IDT70V35/24) & (IDT70V25/24),  
86-pin PGA (IDT70V25/24) and 84-pin PLCC (IDT70V25/24)  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
IDT70V35/34  
– Commercial:15/20/25ns (max.)  
Industrial:20ns  
IDT70V25/24  
– Commercial:15/20/25/35/55ns(max.)  
Industrial:20/25ns  
Low-power operation  
IDT70V35/34S  
IDT70V35/34L  
Active: 430mW (typ.)  
Standby: 3.3mW (typ.)  
Active: 415mW (typ.)  
Standby: 660µW (typ.)  
IDT70V25/24S  
IDT70V25/24L  
Active: 400mW (typ.)  
Standby: 3.3mW (typ.)  
Active: 380mW (typ.)  
Standby: 660µW (typ.)  
Green parts available, see ordering information  
Functional Block Diagram  
R/W  
L
R/W  
R
R
UBL  
UB  
LB  
CE  
OE  
R
LB  
CE  
OE  
L
R
R
L
L
,
(5)  
(5)  
I/O9R-I/O17R  
I/O9L-I/O17L  
I/O  
Control  
I/O  
Control  
(4)  
(4)  
I/O0R-I/O8R  
I/O0L-I/O8L  
(2,3)  
L
(2,3)  
BUSY  
R
BUSY  
(1)  
12R  
(1)  
12L  
A
A
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0L  
A
0R  
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
R
CE  
OE  
L
L
R
R
R/W  
L
SEM  
R
SEM  
INTL  
L
(3)  
(3)  
INTR  
M/S  
5624 drw 01  
NOTES:  
1. A12 is a NC for IDT70V34 and for IDT70V24.  
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
3. BUSY outputs and INT outputs are non-tri-stated push-pull.  
4. I/O0x - I/O7x for IDT70V25/24.  
5. I/O8x - I/O15x for IDT70V25/24.  
OCTOBER 2008  
1
DSC-5624/7  
©2008IntegratedDeviceTechnology,Inc.  

70V24L25G 替代型号

型号 品牌 替代类型 描述 数据表
IDT70V24L25G IDT

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