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70V24S20PFI8 PDF预览

70V24S20PFI8

更新时间: 2024-11-27 14:49:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
25页 226K
描述
Multi-Port SRAM, 4KX16, 20ns, CMOS, PQFP100

70V24S20PFI8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:ObsoleteReach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.92最长访问时间:20 ns
I/O 类型:COMMONJESD-30 代码:S-PQFP-G100
JESD-609代码:e0内存密度:65536 bit
内存集成电路类型:MULTI-PORT SRAM内存宽度:16
湿度敏感等级:3端口数量:2
端子数量:100字数:4096 words
字数代码:4000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:4KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified最大待机电流:0.005 A
最小待机电流:3 V子类别:SRAMs
最大压摆率:0.225 mA标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
Base Number Matches:1

70V24S20PFI8 数据手册

 浏览型号70V24S20PFI8的Datasheet PDF文件第2页浏览型号70V24S20PFI8的Datasheet PDF文件第3页浏览型号70V24S20PFI8的Datasheet PDF文件第4页浏览型号70V24S20PFI8的Datasheet PDF文件第5页浏览型号70V24S20PFI8的Datasheet PDF文件第6页浏览型号70V24S20PFI8的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V  
8/4K x 18 DUAL-PORT  
8/4K x 16 DUAL-PORT  
STATIC RAM  
IDT70V35/34S/L  
IDT70V25/24S/L  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
Features  
– IDT70V25/24S  
IDT70V25/24L  
Active: 380mW (typ.)  
Standby: 660µW (typ.)  
Active: 400mW (typ.)  
Standby: 3.3mW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
IDT70V35/34 (IDT70V25/24) easily expands data bus width  
to 36 bits (32 bits) or more using the Master/Slave select  
when cascading more than one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speedaccess  
IDT70V35  
– Commercial:15/20/25ns(max.)  
– Industrial:20ns  
IDT70V34  
– Commercial:15/20/25ns(max.)  
IDT70V25  
– Commercial:15/20/25/35/55ns(max.)  
– Industrial:20/25ns  
IDT70V24  
BUSY and Interrupt Flag  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
LVTTL-compatible, single 3.3V (±0.3V) power supply  
Available in a 100-pin TQFP (IDT70V35/34) & (IDT70V25/24),  
and 84-pin PLCC (IDT70V25/24)  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
Green parts available, see ordering information  
– Commercial:15/20/25/35/55ns(max.)  
– Industrial:15/20ns  
Low-power operation  
– IDT70V35/34S  
IDT70V35/34L  
Active: 430mW (typ.)  
Standby: 3.3mW (typ.)  
Active: 415mW (typ.)  
Standby: 660µW (typ.)  
Functional Block Diagram  
R/W  
L
R/W  
R
R
UBL  
UB  
LB  
CE  
OE  
R
LB  
CE  
OE  
L
R
R
L
L
,
(5)  
(5)  
I/O9R-I/O17R  
I/O9L-I/O17L  
I/O  
Control  
I/O  
Control  
(4)  
(4)  
I/O0R-I/O8R  
I/O0L-I/O8L  
(2,3)  
L
(2,3)  
BUSY  
R
BUSY  
(1)  
12R  
(1)  
12L  
A
A
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A0L  
A0R  
13  
13  
ARBITRATION  
INTERRUPT  
SEMAPHORE  
LOGIC  
CE  
OE  
R/W  
R
CE  
OE  
R/W  
L
R
L
R
L
SEM  
INTR  
R
SEM  
INTL  
L
(3)  
(3)  
M/S  
NOTES:  
5624 drw 01  
1. A12 is a NC for IDT70V34 and for IDT70V24.  
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
3. BUSY outputs and INT outputs are non-tri-stated push-pull.  
4. I/O0x - I/O7x for IDT70V25/24.  
5. I/O8x - I/O15x for IDT70V25/24.  
NOVEMBER 2017  
1
DSC-5624/9  
©2017 Integrated Device Technology, Inc.  

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