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5V9888NLGI8 PDF预览

5V9888NLGI8

更新时间： 2024-09-17 20:02:11
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
37页 354K
描述
Clock Generator, 500MHz, PQCC28, GREEN, PLASTIC, VFQFPN-28

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5V9888NLGI8 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：GREEN, PLASTIC, VFQFPN-28
针数：28Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.83JESD-30 代码：S-PQCC-N28
JESD-609代码：e3长度：7 mm
湿度敏感等级：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：500 MHz封装主体材料：PLASTIC/EPOXY
封装代码：VQCCN封装等效代码：LCC28,.24SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：400 MHz认证状态：Not Qualified
座面最大高度：1 mm子类别：Clock Generators
最大压摆率：12 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：NO LEAD端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

5V9888NLGI8 数据手册

 浏览型号5V9888NLGI8的Datasheet PDF文件第30页浏览型号5V9888NLGI8的Datasheet PDF文件第31页浏览型号5V9888NLGI8的Datasheet PDF文件第32页浏览型号5V9888NLGI8的Datasheet PDF文件第34页浏览型号5V9888NLGI8的Datasheet PDF文件第35页浏览型号5V9888NLGI8的Datasheet PDF文件第36页 
IDT5V9888  
INDUSTRIALTEMPERATURERANGE  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
RAM(PROGRAMMINGREGISTER)TABLES  
BIT #  
(Default Settings)  
BIT #  
Default  
ADDR  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DESCRIPTION  
Register  
Hex Value  
Configuring Output OUT1  
INV1=Output Inversion for OUT1 ("0"= Non-Invert (Default), "1"=Invert);  
SLEW1=Slew Rate Settings for OUT1 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);  
OEM1= Output Enable Mode for OUT1 output, when used with OE1 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park  
Low, "11"=Park High);  
OEM1[1;0]  
SLEW1[1:0]  
0x1F  
0
0
0
0
0
0
0
0
00  
INV1  
Address 0x1F, Bits 3, 1, 0 are reserved and should be set to "0"  
IP1[2:0]_CONFIG0  
IP1[2:0]_CONFIG1  
IP1[2:0]_CONFIG2  
IP1[2:0]_CONFIG3  
RZ1[3:0]_CONFIG0  
RZ1[3:0]_CONFIG1  
RZ1[3:0]_CONFIG2  
RZ1[3:0]_CONFIG3  
CZ1[3:0]_CONFIG0  
CZ1[3:0]_CONFIG1  
CZ1[3:0]_CONFIG2  
CZ1[3:0]_CONFIG3  
0x20  
0x21  
0x22  
0x23  
0x24  
0x25  
0x26  
0x27  
0x28  
0x29  
0x2A  
0x2B  
0x2C  
0x2D  
0x2E  
0x2F  
0x30  
0x31  
0x32  
0x33  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
ODIV1_CONFIG0  
ODIV1_CONFIG1  
ODIV1_CONFIG2  
ODIV1_CONFIG3  
PLL1 LOOP FILTER SETTING  
Loop Filter Values for PLL1 - For 4 Configurations (Default value is '0');  
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.  
ODIV1_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated  
with PLL1; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;  
Resistor = 0.3KΩ + RZ1[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);  
Zero capacitor = 6pF + CZ1[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);  
Pole capacitor = 1.3pF + CP1[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)  
Charge pump current = 5 * 2^IP1[2:0] µA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;  
CP1[3:0]_CONFIG0  
CP1[3:0]_CONFIG1  
CP1[3:0]_CONFIG2  
CP1[3:0]_CONFIG3  
D1[7:0]_CONFIG0  
D1[7:0]_CONFIG1  
D1[7:0]_CONFIG2  
D1[7:0]_CONFIG3  
N1[7:0]_CONFIG0  
N1[7:0]_CONFIG1  
N1[7:0]_CONFIG2  
N1[7:0]_CONFIG3  
PLL1 INPUT DIVIDER D1 SETTING  
PLL1 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');  
PLL1 MULTIPLIER SETTING  
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.  
N1[11:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');  
A1[3:0]_CONFIGx - Part of PLL1 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');  
SSC_OFFSET1[5:0] - Spread Spectrum Fractional Multiplier Offset Value. See Spread Spectrum Settings in register address range  
0x68-0x6F  
A1[3:0]_CONFIG0  
A1[3:0]_CONFIG1  
A1[3:0]_CONFIG2  
A1[3:0]_CONFIG3  
N1[11:8]_CONFIG0  
N1[11:8]_CONFIG1  
N1[11:8]_CONFIG2  
N1[11:8]_CONFIG3  
Total Multiplier Value M1 = 2 * N1[11:0] + A1 + 1 + SS_OFFSET1 * 1/64  
When A1[3:0] = 0 and spread spectrum disabled, M1= 2 * N1[11:0];  
When A1[3:0] > 0 and spread spectrum disabled, M1 = 2 * N1[11:0] + A1 + 1 ;  
(Note: A < N-1, i.e. valid M values are 2, 4, 6, 8, 9, 10, 11, 12, 13, ..., 4095 assuming within fPFD and fVCO spec);  
PRIMCLK=Priority Selection for Input Clock ("0"=XTALIN/REF_IN becomes Primary (Default), "1"=CLK_IN becomes Primary);  
SM = Switchover Mode ("0x"=Manual, "10"= Auto-NonRevertive, "11"=Auto-Revertive (Default));  
Bit 3 is reserved and should be set to "0".  
SRC2[1:0]  
SRC1[1:0]  
SM[1:0]  
0x34  
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
1
0
46  
55  
00  
PRIMCLK  
SRCx[1:0]=Input Source Selection for Output Dividers "Qx" blocks ("00"=Selected Input CLK, "01"=PLL0, "10"=PLL1, "11"=PLL2);  
Default on SRC1 is the selected input clock. Default on SRC2-6 is PLL0 which will be powered down.  
SRC6[1:0]  
SRC5[1:0]  
SRC4[1:0]  
SRC3[1:0]  
0x35  
0x36  
R
Read-Only  
0x37  
0x38  
0x39  
0x3A  
0x3B  
0x3C  
0x3D  
0x3E  
0x3F  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
00  
00  
00  
IP2[2:0]_CONFIG0  
IP2[2:0]_CONFIG1  
IP2[2:0]_CONFIG2  
IP2[2:0]_CONFIG3  
RZ2[3:0]_CONFIG0  
RZ2[3:0]_CONFIG1  
RZ2[3:0]_CONFIG2  
RZ2[3:0]_CONFIG3  
CZ2[3:0]_CONFIG0  
CZ2[3:0]_CONFIG1  
CZ2[3:0]_CONFIG2  
CZ2[3:0]_CONFIG3  
ODIV2_CONFIG0  
ODIV2_CONFIG1  
ODIV2_CONFIG2  
ODIV2_CONFIG3  
PLL2 LOOP FILTER SETTING  
Loop Filter Values for PLL2 - For 4 Configurations (Default value is '0');  
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.  
ODIV2_CONFIGx=Determines which one of the 2 "Qx-Divider" Configurations to use with, for any of the "Qx-Divider" block associated  
with PLL2; Used in MFC mode; Default ODIV value is "0", and use CONFIG0 of Qx-Divider;  
Resistor = 0.3KΩ + RZ2[3:0] * 1KΩ, 0.3 to 15.3kOhm with 1kOhm Step, ("0000"=0.3kOhm, "0001"=1.3kOhm, "0010"=2.3kOhm, ...);  
Zero capacitor = 6pF + CZ2[3:0] * 27.2pF, 6pF to 414pF with 27.2pF Step, ("0000"=6pF, "0001"=33.2pF, "0010"=60.4pF", ...);  
Pole capacitor = 1.3pF + CP2[3:0] * 0.75pF, 1.3pF to 12.55pF with 0.75pF Step, ("0000"=1.3pF, "0001"=2.05pF, "0010"=2.8pF, ...)  
Charge pump current = 5 * 2^IP2[2:0] µA, 5uA to 640uA with 5, 10, 20, 40, ... binary step;  
CP2[3:0]_CONFIG0  
CP2[3:0]_CONFIG1  
CP2[3:0]_CONFIG2  
CP2[3:0]_CONFIG3  
33  
1...3031323334353637

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