Datasheet > 5V9910A-5SOG

5V9910A-5SOG

更新时间： 2024-01-13 01:35:45

品牌	Logo	应用领域
艾迪悌 - IDT		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
6页	91K
描述
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, GREEN, SOIC-24

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5V9910A-5SOG 技术参数

生命周期：	Obsolete	包装说明：	SOP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.8	系列：	5V
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G24
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	24
实输出次数：	8	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	传播延迟（tpd）：	0.5 ns
Same Edge Skew-Max（tskwd）：	0.5 ns	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子位置：	DUAL
Base Number Matches：	1

5V9910A-5SOG 数据手册

IDT5V9910A

COMMERCIAL AND INDUSTRIAL TEMPERATURE

3.3V LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.

IDT5V^R9^A9^N1^G0^EA^S

3.3V LOW SKEW

PLL CLOCK DRIVER

TURBOCLOCK™ JR.

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JANUARY 27, 2015

FEATURES:

DESCRIPTION:

• Eight zero delay outputs

• <250ps of output to output skew

The IDT5V9910A is a high fanout phase locked-loop clock driver

intended for high performance computing and data-communications

• Selectable positive or negative edge synchronization

• Synchronous output enable

• Output frequency: 15MHz to 85MHz

• 3 skew grades:

IDT5V9910A-2: tSKEW0<250ps

IDT5V9910A-5: tSKEW0<500ps

IDT5V9910A-7: tSKEW0<750ps

• 3-level inputs for PLL range control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• Low Jitter: <200ps peak-to-peak

• Available in SOIC package

• Not Recommended for New Design

• Functional replacement part: 8T49N008-dddNLGI

applications. It has eight zero delay LVTTL outputs.

When the GND/sOE pin is held low, all the outputs are synchronously

enabled. However, if GND/sOE is held high, all the outputs except Q2

and Q3 are synchronously disabled.

Furthermore, when the VCCQ/PE is held high, all the outputs are

synchronized with the positive edge of the REF clock input. When VCCQ/

PE is held low, all the outputs are synchronized with the negative edge

of REF.

The FB signal is compared with the input REF signal at the phase

detector in order to drive the VCO. Phase differences cause the VCO of

the PLL to adjust upwards or downwards accordingly.

An internal loop filter moderates the response of the VCO to the phase

detector. The loop filter transfer function has been chosen to provide

minimal jitter (or frequency variation) while still providing accurate

responses to input frequency changes.

FUNCTIONAL BLOCK DIAGRAM

VCCQ/PE

GND/sOE

PLL

REF

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

MARCH 21, 2014

2014 Integrated Device Technology, Inc.

DSC 5847/3

12 3 4 5 6

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与5V9910A-5SOG相关器件

型号	品牌	描述	获取价格	数据表
5V9910A-5SOGI	IDT	SOIC-24, Tube	获取价格
5V9910A-5SOGI8	IDT	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 I	获取价格
5V9910A-5SOI	IDT	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 I	获取价格
5V9910A-7SO	IDT	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 I	获取价格
5V9910A-7SOG	IDT	PLL Based Clock Driver	获取价格
5V9910A-7SOGI	IDT	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 0.300 I	获取价格

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