Datasheet > 5V991A-7JG8

5V991A-7JG8

更新时间： 2024-01-13 21:31:00

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
8页	74K
描述
PLL Based Clock Driver

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技术参数
数据手册

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5V991A-7JG8 技术参数

生命周期：	Active	包装说明：	QCCJ,
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.77	系列：	5V
输入调节：	STANDARD	JESD-30 代码：	R-PQCC-J32
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	8	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	RECTANGULAR
封装形式：	CHIP CARRIER	Same Edge Skew-Max（tskwd）：	0.75 ns
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	J BEND
端子位置：	QUAD	Base Number Matches：	1

5V991A-7JG8 数据手册

IDT5V991A

COMMERCIAL AND INDUSTRIAL TEMPERATURE

RANGES

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

IDT5V991A

NRND

3.3V PROGRAMMABLE SKEW

PLL CLOCK DRIVER

TURBOCLOCK™

FEATURES:

DESCRIPTION:

• REF is 5V tolerant

The IDT5V991A is a high fanout 3.3V PLL based clock driver

intended for high performance computing and data-communications

applications. A key feature of the programmable skew is the ability of

outputs to lead or lag the REF input signal. The IDT5V991A has eight

programmable skew outputs in four banks of 2. Skew is controlled by

3-level input signals that may be hard-wired to appropriate HIGH-MID-

LOW levels.

• 4 pairs of programmable skew outputs

• Low skew: 200ps same pair, 250ps all outputs

• Selectable positive or negative edge synchronization:

Excellent for DSP applications

• Synchronous output enable

• Output frequency: 3.75MHz to 85MHz

• 2x, 4x, 1/2, and 1/4 outputs

When the GND/sOE pin is held low, all the outputs are synchro-

nously enabled. However, if GND/sOE is held high, all the outputs

except 3Q0 and 3Q1 are synchronously disabled.

• 3 skew grades:

IDT5V991A-2: tSKEW0<250ps

IDT5V991A-5: tSKEW0<500ps

IDT5V991A-7: tSKEW0<750ps

• 3-level inputs for skew and PLL range control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• Low Jitter: <200ps peak-to-peak

• Available in 32-pin PLCC Package

• Not Recommended for New Design

Furthermore, when the VCCQ/PE is held high, all the outputs are

synchronized with the positive edge of the REF clock input. When

VCCQ/PE is held low, all the outputs are synchronized with the negative

edge of REF. Both devices have LVTTL outputs with 12mA balanced

drive outputs.

FUNCTIONAL BLOCK DIAGRAM

GND/sOE

1Q0

Skew

Select

1Q1

1F1:0

2F1:0

3F1:0

4F1:0

VCCQ/PE

2Q0

2Q1

Skew

Select

REF

PLL

3Q0

3Q1

Skew

Select

4Q0

4Q1

Skew

Select

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

NOVEMBER 7, 2013

2013 Integrated Device Technology, Inc.

DSC 5963/3

12 3 4 5 6 7 8

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型号	品牌	描述	获取价格	数据表
5V991A-7JGI	IDT	PLCC-32, Tube	获取价格
5V991A-7JGI8	IDT	PLCC-32, Reel	获取价格
5V991A-7JI	IDT	PLL Based Clock Driver, 5V Series, 4 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC	获取价格
5V993A-2Q	IDT	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28	获取价格
5V993A-2QC	IDT	Clock Driver, PDSO28	获取价格
5V993A-2QG	IDT	PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PDSO28, GREEN,	获取价格