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5V993A-7QGI8 PDF预览

5V993A-7QGI8

更新时间: 2024-11-21 19:53:03
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 111K
描述
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PDSO28, QSOP-28

5V993A-7QGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:QSOP-28针数:28
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
系列:5V输入调节:STANDARD
JESD-30 代码:R-PDSO-G28JESD-609代码:e3
长度:9.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:28实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:0.7 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):1.2 ns
座面最大高度:1.75 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9116 mm最小 fmax:85 MHz
Base Number Matches:1

5V993A-7QGI8 数据手册

 浏览型号5V993A-7QGI8的Datasheet PDF文件第2页浏览型号5V993A-7QGI8的Datasheet PDF文件第3页浏览型号5V993A-7QGI8的Datasheet PDF文件第4页浏览型号5V993A-7QGI8的Datasheet PDF文件第5页浏览型号5V993A-7QGI8的Datasheet PDF文件第6页浏览型号5V993A-7QGI8的Datasheet PDF文件第7页 
3.3V PROGRAMMABLE  
SKEW PLL CLOCK DRIVER  
TURBOCLOCK™  
IDT5V993A  
FEATURES:  
DESCRIPTION:  
• Ref input is 5V tolerant  
The IDT5V993Ais a highfanout3.3VPLLbasedclockdriverintended  
forhighperformancecomputinganddata-communicationsapplications.A  
keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag  
theREFinputsignal.TheIDT5V993Ahassixprogrammableskewoutputs  
andtwozeroskewoutputs.Skewiscontrolledby3-levelinputsignalsthat  
may be hard-wired to appropriate HIGH-MID-LOW levels.  
• 3 pairs of programmable skew outputs  
Low skew: 200ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
• Output frequency: 3.75MHz to 85MHz  
• 2x, 4x, 1/2, and 1/4 outputs  
Whenthe GND/sOE pinis heldlow,allthe outputs are synchronously  
enabled.However,ifGND/sOEisheldhigh,alltheoutputsexcept3Q0and  
3Q1 are synchronously disabled.  
• 3 skew grades:  
IDT5V993A-2: tSKEW0<250ps  
IDT5V993A-5: tSKEW0<500ps  
IDT5V993A-7: tSKEW0<750ps  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
Furthermore, when the VCCQ/PE is held high, all the outputs are  
synchronizedwiththe positive edge ofthe REFclockinput.WhenVCCQ/  
PEis heldlow,allthe outputs are synchronizedwiththe negative edge of  
REF. BothdeviceshaveLVTTLoutputswith12mAbalanceddriveoutputs.  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
Low Jitter: <200ps peak-to-peak  
Available in QSOP package  
FUNCTIONALBLOCKDIAGRAM  
GND/sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
3
3
1F1:0  
2F1:0  
3F1:0  
VCCQ/PE  
2Q0  
2Q1  
Skew  
Select  
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
FS  
4Q0  
4Q1  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
SEPTEMBER 2001  
1
c
2001 Integrated Device Technology, Inc.  
DSC 5408/1  

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