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5V9950PFGI PDF预览

5V9950PFGI

更新时间: 2024-11-21 21:11:03
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
9页 109K
描述
PLL Based Clock Driver, 5V Series, 8 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, TQFP-32

5V9950PFGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:GREEN, TQFP-32针数:32
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
系列:5V输入调节:STANDARD
JESD-30 代码:S-PQFP-G32JESD-609代码:e3
长度:7 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP32,.35SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.5 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:200 MHzBase Number Matches:1

5V9950PFGI 数据手册

 浏览型号5V9950PFGI的Datasheet PDF文件第2页浏览型号5V9950PFGI的Datasheet PDF文件第3页浏览型号5V9950PFGI的Datasheet PDF文件第4页浏览型号5V9950PFGI的Datasheet PDF文件第5页浏览型号5V9950PFGI的Datasheet PDF文件第6页浏览型号5V9950PFGI的Datasheet PDF文件第7页 
JR.  
3.3V PROGRAMMABLE SKEW  
PLL CLOCK DRIVER  
IDT5V9950  
NRND  
TURBOCLOCK™ II JR.  
FEATURES:  
DESCRIPTION:  
• Ref input is 5V tolerant  
The IDT5V9950 is a high fanout 3.3V PLL based clock driver intended  
for high performance computing and data-communications applica-  
tions. A key feature of the programmable skew is the ability of outputs  
to lead or lag the REF input signal. The IDT5V9950 has eight program-  
mable skew outputs in four banks of 2. Skew is controlled by 3-level  
input signals that may be hard-wired to appropriate HIGH-MID-LOW  
levels.  
• 4 pairs of programmable skew outputs  
• Low skew: 185ps same pair, 250ps all outputs  
• Selectable positive or negative edge synchronization:  
Excellent for DSP applications  
• Synchronous output enable  
• Input frequency: 6MHz to 200MHz  
• Output frequency: 6MHz to 200MHz  
• 2x, 4x, 1/2, and 1/4 outputs  
• 3-level inputs for skew and PLL range control  
• PLL bypass for DC testing  
• External feedback, internal loop filter  
• 12mA balanced drive outputs  
• Low Jitter: <100ps cycle-to-cycle  
• Available in TQFP package  
When the sOEpin is held low, all the outputs are synchronously  
enabled. However, if sOEis held high, all the outputs except 2Q0 and  
2Q1 are synchronously disabled.  
Furthermore, when PE is held high, all the outputs are synchronized  
with the positive edge of the REF clock input. When PE is held low, all  
the outputs are synchronized with the negative edge of REF. The  
IDT5V9950 has LVTTL outputs with 12mA balanced drive outputs.  
• Not Recommended for New Design  
FUNCTIONAL BLOCK DIAGRAM  
sOE  
1Q0  
Skew  
Select  
1Q1  
3
3
1F1:0  
2F1:0  
PE TEST  
3
2Q0  
2Q1  
Skew  
Select  
3
3
3
3
REF  
PLL  
FB  
3Q0  
3Q1  
Skew  
Select  
3
3
FS  
3F1:0  
4F1:0  
4Q0  
4Q1  
Skew  
Select  
3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JULY 2012  
1
c
2012 Integrated Device Technology, Inc.  
DSC 5870/7  

5V9950PFGI 替代型号

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