Datasheet > 5V9955BFI

5V9955BFI

更新时间： 2024-11-21 19:24:51

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
11页	129K
描述
Clock Driver, PBGA96

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技术参数
数据手册

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5V9955BFI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	包装说明：	FBGA, BGA96,6X16,32
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.92
JESD-30 代码：	R-PBGA-B96	JESD-609代码：	e0
最大I（ol）：	0.012 A	湿度敏感等级：	3
端子数量：	96	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	FBGA	封装等效代码：	BGA96,6X16,32
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, FINE PITCH
峰值回流温度（摄氏度）：	225	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Clock Drivers
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	20
Base Number Matches：	1

5V9955BFI 数据手册

IDT5V9955

INDUSTRIALTEMPERATURERANGE

3.3VPROGRAMMABLESKEWDUALPLLCLOCKDRIVERTURBOCLOCKW

3.3V PROGRAMMABLE

SKEW DUAL PLL CLOCK

DRIVER TURBOCLOCK™ W

IDT5V9955

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCTOBER 28, 2014

FEATURES:

DESCRIPTION

• Ref input is 5V tolerant

The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended

forhighperformancecomputinganddata-communicationsapplications.A

keyfeatureoftheprogrammableskewistheabilityofoutputstoleadorlag

the REF input signal. The IDT5V9955 has sixteen programmable skew

outputs in eight banks of 2. The two separate PLLs allow the user to

independently control A and B banks. Skew is controlled by 3-level input

signals that may be hard-wired to appropriate HIGH-MID-LOW levels.

The feedback input allows divide-by-functionality from 1 to 12 through

the use of the xDS[1:0] inputs. This provides the user with frequency

multiplication from 1 to 12 without using divided outputs for feedback.

WhenthexsOEpinisheldlow, allthexbankoutputsaresynchronously

enabled. However, ifxsOEisheldhigh, allthexbankoutputsexceptx2Q0

and x2Q1 are synchronously disabled. The xLOCK is high when the

xbank PLL has achieved phase lock.

• 8 pairs of programmable skew outputs

• Two separate A and B banks for individual control

• Low skew: 185ps same pair, 250ps same bank, 350ps both

banks

• Selectable positive or negative edge synchronization on each

bank: excellent for DSP applications

• Synchronous output enable on each bank

• Input frequency: 2MHz to 200MHz

• Output frequency: 6MHz to 200MHz

• 3-level inputs for skew and PLL range control

• 3-level inputs for feedback divide selection multiply / divide

ratios of (1-6, 8, 10, 12) / (2, 4)

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• Low Jitter: <125ps cycle-to-cycle

• Power-down mode on each bank

• Lock indicator on each bank

Furthermore, when xPE is held high, all the outputs are synchronized

withthepositiveedgeoftheREFclockinput. WhenxPEisheldlow, allthe

xbank outputs are synchronized with the negative edge of REF. The

IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.

• Available in BGA package

FUNCTIONALBLOCKDIAGRAM

BLOCK

BPE

BFS

ALOCK

APE

AFS

TEST

REF

BPD

APD

BsOE

AsOE

PLL

/ N

BFB

AFB

BDS1:0

ADS1:0

A1F1:0

B1Q0

B1Q1

A1Q0

A1Q1

Skew

Select

B1F1:0

B2F1:0

B3F1:0

B4F1:0

Select

B2Q0

B2Q1

A2Q0

A2Q1

Skew

Select

Skew

Select

A2F1:0

A3F1:0

A4F1:0

B3Q0

B3Q1

A3Q0

A3Q1

Skew

Select

Skew

Select

B4Q0

B4Q1

A4Q0

A4Q1

Skew

Select

Skew

Select

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JULY 2012

2012 Integrated Device Technology, Inc.

DSC 5974/12

12 3 4 5 6 7...11

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