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5V9888TNLGI8 PDF预览

5V9888TNLGI8

更新时间: 2024-12-01 20:00:23
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
37页 280K
描述
Clock Generator, 500MHz, VFQFPN-28

5V9888TNLGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:VFQFPN-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.79
JESD-30 代码:S-XQCC-N28JESD-609代码:e3
长度:6.3 mm湿度敏感等级:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:500 MHz
封装主体材料:UNSPECIFIED封装代码:QCCN
封装等效代码:LCC28,.24SQ,25封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:400 MHz
认证状态:Not Qualified子类别:Clock Generators
最大压摆率:210 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:6.3 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

5V9888TNLGI8 数据手册

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IDT5V9888T  
3.3V EEPROM  
PROGRAMMABLE CLOCK  
GENERATOR  
FEATURES:  
DESCRIPTION:  
• Three internal PLLs  
The IDT5V9888 is a programmable clock generator intended for high  
performancedata-communications,telecommunications,consumer,and  
networking applications. There are three internal PLLs, each individually  
programmable,allowingforthreeuniquenon-integer-relatedfrequencies.  
The frequencies are generated from a single reference clock. The  
reference clock can come from one of the two redundant clock inputs. A  
glitchless automatic or manual switchover function allows any one of the  
redundant clocks to be selected during normal operation.  
• Internal non-volatile EEPROM  
• JTAG and FAST mode I2C serial interfaces  
• Input Frequency Ranges: 1MHz to 400MHz  
• Output Frequency Ranges:  
LVTTL: up to 200MHz  
LVPECL/ LVDS: up to 500MHz  
• Reference Crystal Input with programmable oscillator gain and  
programmable linear load capacitance  
Crystal Frequency Range: 8MHz to 50MHz  
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider  
• 10-bit post-divider blocks  
• Fractional Dividers  
• Two of the PLLs support Spread Spectrum Generation  
capability  
• I/O Standards:  
Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS  
Inputs - 3.3V LVTTL/ LVCMOS  
• Programmable Slew Rate Control  
• Programmable Loop Bandwidth Settings  
• Programmable output inversion to reduce bimodal jitter  
• Redundant clock inputs with glitchless auto and manual  
switchover options  
TheIDT5V9888canbeprogrammedthroughtheuseoftheI2CorJTAG  
interfaces. The programming interface enables the device to be pro-  
grammedwhenitisinnormaloperationorwhatiscommonlyknownasin-  
systemprogrammable. AninternalEEPROMallowstheusertosaveand  
restore the configuration of the device without having to reprogram it on  
power-up. JTAG boundary scan is also implemented.  
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback  
divider. Thisallowstheusertogeneratethreeuniquenon-integer-related  
frequencies. The PLL loop bandwidth is programmable to allow the user  
totailorthePLLresponsetotheapplication. Forinstance,theusercantune  
the PLL parameters to minimize jitter generation or to maximize jitter  
attenuation. Spread spectrum generation and fractional divides are  
allowed on two of the PLLs.  
Thereare10-bitpostdividersonfiveofthesixoutputbanks. Twoofthe  
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The  
otherfouroutputbanksareLVTTL. TheoutputsareconnectedtothePLLs  
via the switch matrix. The switch matrix allows the user to route the PLL  
outputstoanyoutputbank. Thisfeaturecanbeusedtosimplifyandoptimize  
the board layout. In addition, each output's slew rate and enable/disable  
function can be programmed.  
• JTAG Boundary Scan  
• Individual output enable/disable  
• Power-down mode  
• 3.3VVDD  
• Available in TQFP and VFQFPN packages  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JUNE 2010  
1
c
2010 Integrated Device Technology, Inc.  
DSC 7044/13  

5V9888TNLGI8 替代型号

型号 品牌 替代类型 描述 数据表
5V9888TNLGI IDT

完全替代

Clock Generator, 500MHz, VFQFPN-28

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