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5V9888NLGI8

更新时间： 2024-01-04 01:35:02
品牌 Logo 应用领域
艾迪悌 - IDT 时钟外围集成电路晶体
页数 文件大小 规格书
37页 354K
描述
Clock Generator, 500MHz, PQCC28, GREEN, PLASTIC, VFQFPN-28

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5V9888NLGI8 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：GREEN, PLASTIC, VFQFPN-28
针数：28Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.83JESD-30 代码：S-PQCC-N28
JESD-609代码：e3长度：7 mm
湿度敏感等级：1端子数量：28
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：500 MHz封装主体材料：PLASTIC/EPOXY
封装代码：VQCCN封装等效代码：LCC28,.24SQ,25
封装形状：SQUARE封装形式：CHIP CARRIER, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：400 MHz认证状态：Not Qualified
座面最大高度：1 mm子类别：Clock Generators
最大压摆率：12 mA最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn) - annealed
端子形式：NO LEAD端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

5V9888NLGI8 数据手册

 浏览型号5V9888NLGI8的Datasheet PDF文件第31页浏览型号5V9888NLGI8的Datasheet PDF文件第32页浏览型号5V9888NLGI8的Datasheet PDF文件第33页浏览型号5V9888NLGI8的Datasheet PDF文件第35页浏览型号5V9888NLGI8的Datasheet PDF文件第36页浏览型号5V9888NLGI8的Datasheet PDF文件第37页 
IDT5V9888  
3.3V EEPROMPROGRAMMABLECLOCKGENERATOR  
INDUSTRIALTEMPERATURERANGE  
RAM(PROGRAMMINGREGISTER)TABLES  
BIT #  
(Default Settings)  
BIT #  
Default  
ADDR  
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DESCRIPTION  
Register  
Hex Value  
0x40  
0x41  
0x42  
0x43  
0x44  
0x45  
0x46  
0x47  
0x48  
0x49  
0x4A  
0x4B  
0x4C  
0x4D  
0x4E  
0x4F  
0x50  
0x51  
0x52  
0x53  
0x54  
0x55  
0x56  
0x57  
0x58  
0x59  
0x5A  
0x5B  
0x5C  
0x5D  
0x5E  
0x5F  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
00  
BB  
00  
00  
00  
BB  
00  
00  
0C  
BB  
00  
00  
0C  
BB  
00  
00  
03  
BB  
00  
00  
D2[7:0]_CONFIG0  
D2[7:0]_CONFIG1  
D2[7:0]_CONFIG2  
D2[7:0]_CONFIG3  
N2[7:0]_CONFIG0  
N2[7:0]_CONFIG1  
N2[7:0]_CONFIG2  
N2[7:0]_CONFIG3  
PLL2 INPUT DIVIDER D2 SETTING  
PLL2 D-Divider Values (Prescaler) - For 4 Configurations (Default value is '0');  
PLL2 MULTIPLIER SETTING  
CONFIG0 will be selected if GINx are disabled and operating in MFC mode.  
N2[11:0]_CONFIGx - Part of PLL2 M Integer Feedback Divider Values (see equation below) - For 4 Configurations (Default value is '0');  
Total Multiplier Value M2 = N2;  
N2[11:8]_CONFIG0  
N2[11:8]_CONFIG1  
N2[11:8]_CONFIG2  
N2[11:8]_CONFIG3  
INV2  
Bits [7:4] in addresses 0x48, 0x49, 0x4A, and 0x4B are reserved and should be set to "0"  
OEM2[1:0]  
SLEW2[1:0]  
Configuring Output OUT2  
INV2=Output Inversion for OUT2 ("0"= Non-Invert (Default), "1"=Invert);  
SLEW2=Slew Rate Settings for OUT2 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);  
OEM2= Output Enable Mode for OUT2output, when used with OE2 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park  
Low, "11"=Park High);  
Q2[x:x]=Output Divider "Q2" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;  
PM2[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));  
(Note: To enable OUT2, PM2 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)  
Q2[1:0]_CONFIG1  
PM2[1:0]_CONFIG1  
Q2[1:0]_CONFIG0  
PM2[1:0]_CONFIG0  
Q2[9:2]_CONFIG0  
Address 0x4C, Bits 3, 1, 0 are reserved and should be set to "0"  
Q2[9:2]_CONFIG1  
OEM3[1:0]  
SLEW3[1:0]  
INV3  
Configuring Output OUT3  
INV3=Output Inversion for OUT3 ("0"= Non-Invert (Default), "1"=Invert);  
SLEW3=Slew Rate Settings for OUT3 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);  
OEM3= Output Enable Mode for OUT3 output, when used with OE3 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park  
Low, "11"=Park High);  
Q3[x:x]=Output Divider "Q3" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;  
PM3[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));  
(Note: To enable OUT3, PM3 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)  
Q3[1:0]_CONFIG1  
PM3[1:0]_CONFIG1  
Q3[1:0]_CONFIG0  
PM3[1:0]_CONFIG0  
Q3[9:2]_CONFIG0  
Address 0x50, Bits 3, 1, 0 are reserved and should be set to "0"  
Q3[9:2]_CONFIG1  
OEM4[1:0]  
SLEW4[1:0]  
LVL4[1:0]  
INV4_1  
INV4_0  
Configuring Output OUT4  
INV4_1=Output Inversion for /OUT4 ("0"= Invert , "1"=Non-Invert (Default));  
INV4_0=Output Inversion for OUT4 ("0"= Invert , "1"=Non-Invert (Default));  
SLEW4=Slew Rate Settings for OUT4 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);  
OEM4= Output Enable Mode for OUT4 output, when used with OE4 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park  
Low, "11"=Park High);  
LVL4=Output IO Standard Selection, ("00"=LVTTL (Default), "01"=LVDS, "10"=LVPECL, "11"=Reserved);  
Q4[x:x]=Output Divider "Q4" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;  
PM4[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));  
(Note: To enable OUT4, PM4 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)  
Q4[1:0]_CONFIG1  
PM4[1:0]_CONFIG1  
Q4[1:0]_CONFIG0  
PM4[1:0]_CONFIG0  
Q4[9:2]_CONFIG0  
When using LVPECL or LVDS outputs, SLEW4 must be set to "00".  
Q4[9:2]_CONFIG1  
OEM5[1:0]  
SLEW5[1:0]  
LVL5[1:0]  
INV5_1  
INV5_0  
Configuring Output OUT5  
INV5_1=Output Inversion for /OUT5 ("0"= Invert, "1"=Non-Invert (Default));  
INV5_0=Output Inversion for OUT5 ("0"= Invert, "1"=Non-Invert (Default));  
SLEW5=Slew Rate Settings for OUT5 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);  
OEM5= Output Enable Mode for OUT5 output, when used with OE5 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park  
Low, "11"=Park High);  
LVL5=Output IO Standard Selection, ("00"=LVTTL (Default), "01"=LVDS, "10"=LVPECL, "11"=Reserved);  
Q5[x:x]=Output Divider "Q5" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;  
PM5[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));  
(Note: To enable OUT5, PM5 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)  
Q5[1:0]_CONFIG1  
PM5[1:0]_CONFIG1  
Q5[1:0]_CONFIG0  
PM5[1:0]_CONFIG0  
Q5[9:2]_CONFIG0  
When using LVPECL or LVDS outputs, SLEW5 must be set to "00".  
Q5[9:2]_CONFIG1  
OEM6[1:0]  
SLEW6[1:0]  
INV6  
Configuring Output OUT6  
INV6=Output Inversion for OUT6 ("0"= Non-Invert (Default), "1"=Invert);  
SLEW6=Slew Rate Settings for OUT6 output ("00"= 2.75V/ns (Default), "01"=2V/ns, "10"=1.25V/ns, "11"=0.7V/ns);  
OEM6= Output Enable Mode for OUT6 output, when used with OE6 bit and SHUTDOWN/OE pin ("0x" = Tri-state (Default), "10"=Park  
Low, "11"=Park High);  
Q6[x:x]=Output Divider "Q6" Values (Default value is '2') - Support 2 output configurations when used in MFC mode;  
PM6[x:x]=Divide Mode, ("00"=Divider Disabled;"01"=Divide by '1';"10"=Divide by 2; "11"=Divide by (Q+2) (Default));  
(Note: To enable OUT6, PM6 register bit values for both CONFIG0 and CONFIG1 configurations must be non-zero.)  
Q6[1:0]_CONFIG1  
PM6[1:0]_CONFIG1  
Q6[1:0]_CONFIG0  
PM6[1:0]_CONFIG0  
Q6[9:2]_CONFIG0  
Address 0x5C, Bits 3 is reserved and should be set to "0"  
Address 0x5C, Bits 1, 0 are reserved and should be set to "1"  
Q6[9:2]_CONFIG1  
34  
1...31323334353637

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