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5V9351PFGI8 PDF预览

5V9351PFGI8

更新时间: 2024-11-30 21:15:27
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
10页 96K
描述
PLL Based Clock Driver, 5V Series, 9 True Output(s), 0 Inverted Output(s), PQFP32, GREEN, TQFP-32

5V9351PFGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:GREEN, TQFP-32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
其他特性:ALSO OPERATES AT 3.3V SUPPLY系列:5V
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G32
JESD-609代码:e3长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:32实输出次数:9
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1.6 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:7 mm
最小 fmax:100 MHzBase Number Matches:1

5V9351PFGI8 数据手册

 浏览型号5V9351PFGI8的Datasheet PDF文件第2页浏览型号5V9351PFGI8的Datasheet PDF文件第3页浏览型号5V9351PFGI8的Datasheet PDF文件第4页浏览型号5V9351PFGI8的Datasheet PDF文件第5页浏览型号5V9351PFGI8的Datasheet PDF文件第6页浏览型号5V9351PFGI8的Datasheet PDF文件第7页 
LOW VOLTAGE PLL  
CLOCK DRIVER  
IDT5V9351  
FEATURES:  
DESCRIPTION:  
• Fully integrated PLL  
The IDT5V9351is a highperformance, zerodelay, lowskew, phase-lock  
loop (PLL) clock driver. It has four banks of configurable outputs. The  
IDT5V9351usesadifferentialPECLreferenceinputandanexternalfeedback  
input. These features allow the IDT5V9351 to be used as a zero delay, low  
skewfan-outbuffer. REF_SELallowsselectionbetweenPECLinputorTCLK,  
a CMOS clock driver input.  
• Output frequency up to 200MHz  
• 2.5V and 3.3V Compatible  
• Compatible with PowerPC, Intel, and high performance RISC  
microprocessors  
• Output frequency configurable  
• Cycle-to-cycle jitter max. 22ps RMS  
• Compatible with MPC9351  
IfPLL_ENissettolowandREF_SELtohigh,itwillbypassthePLL. Bydoing  
so,theIDT5V9351willbeinclockbuffermode. AnyclockappliedtoTCLKwill  
be divideddowntofouroutputbanks.  
Available in TQFP package  
WhenPLL_ENis sethigh,PLLis enabled. AnyclockappliedtoTCLKwill  
beclockedinbothphaseandfrequencytoFBIN. PECLclockisactivatedby  
settingREF_SELtolow.  
FUNCTIONALBLOCKDIAGRAM  
(pullup)  
PECL_CLK  
0
0
1
PECL_CLK  
÷2  
÷4  
÷8  
0
1
REF  
(pulldown)  
D
D
D
D
Q
Q
Q
Q
1
QA  
tCLK  
REF_SEL  
FBIN  
(pulldown)  
(pulldown)  
PLL  
FB  
200 - 400MHz  
0
1
QB  
(pullup)  
PLL_En  
QC0  
QC1  
0
1
(pulldown)  
fSELA  
fSELB  
fSELC  
fSELD  
(pulldown)  
(pulldown)  
QD0  
QD1  
QD2  
QD3  
QD4  
0
1
(pulldown)  
(pulldown)  
OE  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MARCH 2003  
1
© 2003 Integrated Device Technology, Inc.  
DSC-5972/18  

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