Datasheet > 5V9352PFGI

5V9352PFGI

更新时间： 2024-01-17 21:19:33

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
12页	116K
描述
TQFP-32, Tray

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5V9352PFGI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	TQFP
包装说明：	GREEN, TQFP-32	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.82
其他特性：	ALSO OPERATES AT 3.3V SUPPLY	系列：	5V
输入调节：	STANDARD	JESD-30 代码：	S-PQFP-G32
JESD-609代码：	e3	长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	32	实输出次数：	11
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.2 ns	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	2.625 V	最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	7 mm	最小 fmax：	100 MHz
Base Number Matches：	1

5V9352PFGI 数据手册

IDT5V9352

3.3V/2.5VPHASE-LOCKLOOPCLOCKDRIVERZERODELAYBUFFER

INDUSTRIALTEMPERATURERANGE

IDT5V9352

3.3V/2.5V PHASE-LOCK LOOP CLOCK

DRIVER ZERO DELAY BUFFER

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCT 28, 2014

FEATURES:

The 5V9352 features three banks of individually configurable outputs.

The banks are configured with five, four, and two outputs. The internal

dividecircuitryallowsforoutputfrequencyratiosof1:1, 2:1, 3:1, and3:2:1.

The output frequency relationship is controlled by the fSEL frequency

control pins. The fSEL pins, as well as other inputs, are LVCMOS/LVTTL

compatibleinputs

• Phase-lock loop clock distribution for high performance clock

tree applications

• Output enable bank control

• External feedback (FBIN) pin is used to synchronize the

outputs to the clock input signal

Unlike many products containing PLLs, the 5V9352 does not require

external RC networks. The loop filter for the PLL is included on-chip,

minimizing component count, board space, and cost.

• No external RC network required for PLL loop stability

• Operates at 3.3V/2.5V VCC

• Spread Spectrum Compatible

BecauseitisbasedonPLLcircuitry, the5V9352requiresastabilization

time to achieve phase lock of the feedback signal to the reference signal.

This stabilization time is required, following power up and application of a

fixed-frequency, fixed-phase signal at REFCLK, as well as following any

changes to the PLL reference or feedback signals. The PLL can be

bypassed for test purposes by setting the PLL_EN to high.

The 5V9352 is available in Industrial temperature range (-40°C to

+85°C).

• Operating frequency up to 200MHz

• Compatible with Motorola MPC9352

• Available in 32-pin TQFP package

• Use replacement part: 87952AYILF

DESCRIPTION:

The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver

targeted for high performance clock tree applications. It uses a PLL to

preciselyalign, inbothfrequencyandphase. The5V9352operatesat2.5V

and 3.3V.

FUNCTIONALBLOCKDIAGRAM

BANK A

QA0

CCLK

REFCLK

FBIN

REF

Q^A1

Q^A2

VCO

PLL

Q^A3

Q^A4

PLL_En

VCO_^SEL

fSELA

BANK B

QB0

Q^B1

Q^B2

QB3

fSELB

fSELC

BANK C

Q^C0

QC1

MR/OE

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

MAY 2013

2003 Integrated Device Technology, Inc.

DSC 5973/19

12 3 4 5 6 7...12

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