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5V9882TPGGI PDF预览

5V9882TPGGI

更新时间: 2024-11-30 21:21:15
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
31页 211K
描述
Clock Generator, 500MHz, PDSO16, GREEN, TSSOP-16

5V9882TPGGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm湿度敏感等级:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:500 MHz
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:400 MHz
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Clock Generators最大压摆率:110 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

5V9882TPGGI 数据手册

 浏览型号5V9882TPGGI的Datasheet PDF文件第2页浏览型号5V9882TPGGI的Datasheet PDF文件第3页浏览型号5V9882TPGGI的Datasheet PDF文件第4页浏览型号5V9882TPGGI的Datasheet PDF文件第5页浏览型号5V9882TPGGI的Datasheet PDF文件第6页浏览型号5V9882TPGGI的Datasheet PDF文件第7页 
IDT5V9882T  
3.3V EEPROM  
PROGRAMMABLE CLOCK  
GENERATOR  
FEATURES:  
DESCRIPTION:  
• Three internal PLLs  
TheIDT5V9882Tisaprogrammableclockgeneratorintendedforhigh  
performancedata-communications,telecommunications,consumer,and  
networking applications. There are three internal PLLs, each individually  
programmable,allowingforthreeuniquenon-integer-relatedfrequencies.  
The frequencies are generated from a single reference clock. The  
reference clock can come from one of the two redundant clock inputs. A  
glitchless automatic or manual switchover function allows any one of the  
redundant clocks to be selected during normal operation.  
• Internal non-volatile EEPROM  
• FAST mode I2C serial interfaces  
• Input Frequency Ranges: 1MHz to 400MHz  
• Output Frequency Ranges: 4.9kHz to 500MHz  
• Reference Crystal Input with programmable oscillator gain and  
programmable linear load capacitance  
Crystal Frequency Range: 8MHz to 50MHz  
• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider  
• 10-bit post-divider blocks  
The IDT5V9882T can be programmed through the use of the I2C  
interfaces. The programming interface enables the device to be pro-  
grammedwhenitisinnormaloperationorwhatiscommonlyknownasin-  
systemprogrammable. AninternalEEPROMallowstheusertosaveand  
restore the configuration of the device without having to reprogram it on  
power-up.  
• Fractional Dividers  
• Two of the PLLs support Spread Spectrum Generation  
capability  
• I/O Standards:  
Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS  
Inputs - 3.3V LVTTL/ LVCMOS  
• Programmable Slew Rate Control  
• Programmable Loop Bandwidth Settings  
• Programmable output inversion to reduce bimodal jitter  
• Individual output enable/disable  
• Power-down mode  
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback  
divider. Thisallowstheusertogeneratethreeuniquenon-integer-related  
frequencies. The PLL loop bandwidth is programmable to allow the user  
totailorthePLLresponsetotheapplication. Forinstance,theusercantune  
the PLL parameters to minimize jitter generation or to maximize jitter  
attenuation. Spread spectrum generation and fractional divides are  
allowed on two of the PLLs.  
• 3.3VVDD  
• Available in TSSOP package  
Thereare10-bitpostdividersonfiveofthesixoutputbanks. Twoofthe  
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The  
otherfouroutputbanksareLVTTL. TheoutputsareconnectedtothePLLs  
via the switch matrix. The switch matrix allows the user to route the PLL  
outputstoanyoutputbank. Thisfeaturecanbeusedtosimplifyandoptimize  
the board layout. In addition, each output's slew rate and enable/disable  
function can be programmed.  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
JUNE 2010  
1
c
2010 Integrated Device Technology, Inc.  
DSC 7064/2  

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