Datasheet > 5V9885CNLGI

5V9885CNLGI

更新时间： 2024-01-25 06:36:55

品牌	Logo	应用领域
艾迪悌 - IDT		时钟外围集成电路晶体
页数	文件大小	规格书
39页	295K
描述
Clock Generator, 500MHz, VFQFPN-28

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5V9885CNLGI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFN	包装说明：	VFQFPN-28
针数：	28	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.83	JESD-30 代码：	S-XQCC-N28
JESD-609代码：	e3	长度：	6 mm
湿度敏感等级：	1	端子数量：	28
最高工作温度：	85 °C	最低工作温度：	-40 °C
最大输出时钟频率：	500 MHz	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC28,.24SQ,25
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
主时钟/晶体标称频率：	50 MHz	认证状态：	Not Qualified
座面最大高度：	1 mm	子类别：	Clock Generators
最大压摆率：	110 mA	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	NO LEAD	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	6 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

5V9885CNLGI 数据手册

IDT5V9885C

INDUSTRIALTEMPERATURERANGE

3.3V EEPROMPROGRAMMABLECLOCKGENERATOR

IDT5V9885C

3.3V EEPROM

PROGRAMMABLE CLOCK

GENERATOR

FEATURES:

DESCRIPTION:

• Three internal PLLs

TheIDT5V9885Cisaprogrammableclockgeneratorintendedforhigh

performancedata-communications,telecommunications,consumer,and

networking applications. There are three internal PLLs, each individually

programmable,allowingforthreeuniquenon-integer-relatedfrequencies.

The frequencies are generated from a single reference clock. The

reference clock can come from one of the two redundant clock inputs. A

glitchless automatic or manual switchover function allows any one of the

redundant clocks to be selected during normal operation.

• Internal non-volatile EEPROM

• JTAG and FAST mode I²C serial interfaces

• Input Frequency Ranges: 1MHz to 400MHz

• Output Frequency Ranges: 4.9kHz to 500MHz

• Reference Crystal Input with programmable oscillator gain and

programmable linear load capacitance

− Crystal Frequency Range: 8MHz to 50MHz

• Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider

• 10-bit post-divider blocks

The IDT5V9885C can be programmed through the use of the I²C or

JTAG interfaces. The programming interface enables the device to be

programmedwhenitisinnormaloperationorwhatiscommonlyknownas

in-system programmable. An internal EEPROM allows the user to save

and restore the configuration of the device without having to reprogram it

on power-up. JTAG boundary scan is also implemented.

• Fractional Dividers

• Two of the PLLs support Spread Spectrum Generation

capability

• I/O Standards:

− Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS

− Inputs - 3.3V LVTTL/ LVCMOS

• Programmable Slew Rate Control

• Programmable Loop Bandwidth Settings

• Programmable output inversion to reduce bimodal jitter

• Redundant clock inputs with glitchless auto and manual

switchover options

Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback

divider. Thisallowstheusertogeneratethreeuniquenon-integer-related

frequencies. The PLL loop bandwidth is programmable to allow the user

totailorthePLLresponsetotheapplication. Forinstance,theusercantune

the PLL parameters to minimize jitter generation or to maximize jitter

attenuation. Spread spectrum generation and fractional divides are

allowed on two of the PLLs.

• JTAG Boundary Scan

• Individual output enable/disable

• Power-down mode

Thereare10-bitpostdividersonfiveofthesixoutputbanks. Twoofthe

six output banks are configurable to be LVTTL, LVPECL, or LVDS. The

otherfouroutputbanksareLVTTL. TheoutputsareconnectedtothePLLs

via the switch matrix. The switch matrix allows the user to route the PLL

outputstoanyoutputbank. Thisfeaturecanbeusedtosimplifyandoptimize

the board layout. In addition, each output's slew rate and enable/disable

function can be programmed.

• 3.3VVDD

• Available in TQFP and VFQFPN packages

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

DECEMBER 2009

2009 Integrated Device Technology, Inc.

DSC 7117/4

12 3 4 5 6 7...39

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