Datasheet > 5V9351PFI

5V9351PFI

更新时间： 2024-02-28 22:21:57

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
10页	96K
描述
Clock Driver

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技术参数
数据手册

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5V9351PFI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
风险等级：	5.87	JESD-609代码：	e0
湿度敏感等级：	3	端子面层：	Tin/Lead (Sn85Pb15)
Base Number Matches：	1

5V9351PFI 数据手册

IDT5V9351

LOWVOLTAGEPLLCLOCKDRIVER

INDUSTRIALTEMPERATURERANGE

LOW VOLTAGE PLL

CLOCK DRIVER

IDT5V9351

FEATURES:

DESCRIPTION:

• Fully integrated PLL

The IDT5V9351is a highperformance, zerodelay, lowskew, phase-lock

loop (PLL) clock driver. It has four banks of configurable outputs. The

IDT5V9351usesadifferentialPECLreferenceinputandanexternalfeedback

input. These features allow the IDT5V9351 to be used as a zero delay, low

skewfan-outbuffer. REF_SELallowsselectionbetweenPECLinputorTCLK,

a CMOS clock driver input.

• Output frequency up to 200MHz

• 2.5V and 3.3V Compatible

• Compatible with PowerPC™, Intel, and high performance RISC

microprocessors

• Output frequency configurable

• Cycle-to-cycle jitter max. 22ps RMS

• Compatible with MPC9351

IfPLL_ENissettolowandREF_SELtohigh,itwillbypassthePLL. Bydoing

so,theIDT5V9351willbeinclockbuffermode. AnyclockappliedtoTCLKwill

be divideddowntofouroutputbanks.

• Available in TQFP package

WhenPLL_ENis sethigh,PLLis enabled. AnyclockappliedtoTCLKwill

beclockedinbothphaseandfrequencytoFBIN. PECLclockisactivatedby

settingREF_SELtolow.

FUNCTIONALBLOCKDIAGRAM

(pullup)

PECL_CLK

÷2

÷4

÷8

REF

(pulldown)

tCLK

REF_SEL

FBIN

(pulldown)

PLL

200 - 400MHz

(pullup)

PLL_En

QC0

QC1

(pulldown)

fSELA

fSELB

fSELC

fSELD

(pulldown)

QD0

QD1

QD2

QD3

QD4

(pulldown)

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

MARCH 2003

DSC-5972/18

12 3 4 5 6 7...10

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