Datasheet > 5T929-30NLI8

5T929-30NLI8

更新时间： 2024-11-24 21:11:15

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
9页	152K
描述
Clock Driver, PQCC28

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中文翻译

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技术参数
数据手册

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5T929-30NLI8 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.92	JESD-30 代码：	S-PQCC-N28
JESD-609代码：	e0	湿度敏感等级：	1
端子数量：	28	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCN	封装等效代码：	LCC28,.24SQ,25
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	225	电源：	2.5/3.3 V
认证状态：	Not Qualified	子类别：	Clock Drivers
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	NO LEAD
端子节距：	0.635 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	Base Number Matches：	1

5T929-30NLI8 数据手册

IDT5T929

INDUSTRIALTEMPERATURERANGE

PRECISIONCLOCKGENERATOROC-48APPLICATIONS

IDT5T929

PRECISION CLOCK GENERATOR

OC-48 APPLICATIONS

FEATURES:

DESCRIPTION:

• Input frequency:

The IDT5T929 generates a high precision FEC (Forward Error Cor-

rection) or non-FEC source clock for SONET/SDH systems as well as a

source clock for Gigabit Ethernet systems. This device also has clock

regeneration capability: it creates a "clean" version of the clock input by

using the internal oscillator to square the input clock's rising and falling

edges and remove jitter. In the event that the main clock input fails, the

device automatically locks to a backup reference clock using a hitless

switchover mechanism.

- ForSONETnon-FEC:19.44MHz,38.88MHz,77.76MHz,155.52MHz,

311.04MHz, or 622.08MHz

- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,

333.26MHz, or 666.52MHz

- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,

312.5MHz, or 625MHz

- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,

322.26MHz, or 644.53MHz

• Output frequency range selection

• 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT

• Regenerated input clock on QREG

• Lock indicator

• Power-down mode

• LVPECL or LVDS outputs

This device detects loss ofvalidCLKINandleaves the VCOofthe PLLat

thelastvalidfrequencywhileanalternateinputREFINis selected. IfCLKIN

andREFINaredifferentfrequencies,themultiplicationfactorwillbeadjustedto

retainthesameoutputfrequency.

TheIDT5T929canactasatranslatorfromadifferentialLVPECL,LVDS,or

single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T929-10

has LVDSoutputs andthe IDT5T929-30has LVPECLoutputs.

ThetwomodesofoutputfrequencyrangearecontrolledbytheSELmode.

WhenSELmodeishighorlow,theQ^OUTisamultipliedversionoftheinputclock

while QREG is a regeneratedversionofthe inputclock.

• Two modes of output frequency range

- Mode0:QOUT range155.5-166.6MHz. QREG isaregeneratedversion

ofthe inputclock.

- Mode 1: QOUT range 622 - 666.5MHz. QREG is a regenerated version

ofthe inputclockfrequency.

• Hitless switchover

• Differential LVPECL, LVDS, or single-ended LVTTL input interface

• 2.375 - 3.465V core and I/O

• Available in VFQFPN package

APPLICATIONS:

• Terabit routers

• Gigabit ethernet systems

• SONET / SDH systems

• Digital cross connects

• Optical transceiver modules

FUNCTIONALBLOCKDIAGRAM

QREG

CLKIN

INPUT

MUX

DIVN

QREG

PLL

QOUT

DIVM

CONTROL

LOGIC

LOCK,

FREQ.

DETECTOR

REFIN

SELMODE

LOCK

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

NOVEMBER 2004

2004 Integrated Device Technology, Inc.

DSC 6400/17

12 3 4 5 6 7...9

中文翻译

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与5T929-30NLI8相关器件

型号	品牌	获取价格	描述	数据表
5T9302PGGI	IDT	获取价格	Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 1
5T9302PGGI8	IDT	获取价格	Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 1
5T9302PGI	IDT	获取价格	Clock Driver, 5T Series, 2 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 1
5T9304	IDT	获取价格	LVDS, 1:4 Clock Buffer Terabuffer
5T9304_15	IDT	获取价格	LVDS, 1:4 Clock Buffer Terabuffer
5T9304EJGI	IDT	获取价格	LVDS, 1:4 Clock Buffer Terabuffer
5T9304EJI	IDT	获取价格	Low Skew Clock Driver, 5T Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7
5T9304I	IDT	获取价格	LVDS, 1:4 Clock Buffer Terabuffer
5T9304PG	IDT	获取价格	Low Skew Clock Driver, 5T Series, 8 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 X 7
5T9304PGG	IDT	获取价格	LVDS, 1:4 Clock Buffer Terabuffer

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