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2N5196 PDF预览

2N5196

更新时间: 2024-11-08 22:45:03
品牌 Logo 应用领域
威世 - VISHAY /
页数 文件大小 规格书
6页 60K
描述
Monolithic N-Channel JFET Duals

2N5196 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
风险等级:5.79FET 技术:JUNCTION
JESD-609代码:e0最高工作温度:200 °C
极性/信道类型:N-CHANNEL最大功率耗散 (Abs):0.25 W
子类别:FET General Purpose Small Signal表面贴装:NO
端子面层:Tin/Lead (Sn/Pb)Base Number Matches:1

2N5196 数据手册

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2N5196/5197/5198/5199  
Vishay Siliconix  
Monolithic N-Channel JFET Duals  
PRODUCT SUMMARY  
Part Number VGS(off) (V) V(BR)GSS Min (V) gfs Min (mS) IG Max (pA) VGS1 – VGS2Max (mV)  
2N5196  
2N5197  
2N5198  
2N5199  
–0.7 to –4  
–0.7 to –4  
–0.7 to –4  
–0.7 to –4  
–50  
–50  
–50  
–50  
1
1
1
1
–15  
–15  
–15  
–15  
5
5
10  
15  
FEATURES  
BENEFITS  
APPLICATIONS  
D Monolithic Design  
D High Slew Rate  
D Tight Differential Match vs. Current  
D Wideband Differential Amps  
D Improved Op Amp Speed, Settling Time  
D High-Speed, Temp-Compensated,  
Accuracy  
Single-Ended Input Amps  
D Low Offset/Drift Voltage  
D Low Gate Leakage: 5 pA  
D Low Noise  
D Minimum Input Error/Trimming Requirement  
D Insignificant Signal Loss/Error Voltage  
D High System Sensitivity  
D High Speed Comparators  
D Impedance Converters  
D High CMRR: 100 dB  
D Minimum Error with Large Input Signal  
DESCRIPTION  
The 2N5196/5197/5198/5199 JFET duals are designed for  
high-performance differential amplification for a wide range of  
precision test instrumentation applications. This series  
features tightly matched specs, low gate leakage for accuracy,  
and wide dynamic range with IG guaranteed at VDG = 20 V.  
The hermetically-sealed TO-71 package is available with full  
military processing (see Military Information and the  
2N5545/5546/5547JANTX/JANTXV data sheet).  
For similar products see the low-noise U/SST401 series, the  
high-gain 2N5911/5912, and the low-leakage U421/423 data  
sheets.  
TO-71  
S
G
2
1
1
3
6
4
D
1
D
2
2
5
G
1
S
2
Top View  
ABSOLUTE MAXIMUM RATINGS  
a
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 V  
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Power Dissipation :  
Notes  
Per Side . . . . . . . . . . . . . . . . . . . . . . . . 250 mW  
b
Total . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW  
1
Lead Temperature ( / ” from case for 10 sec.) . . . . . . . . . . . . . . . . . . 300 _C  
16  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 200_C  
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . –55 to 150_C  
a. Derate 2 mW/_C above 85_C  
b. Derate 4 mW/_C above 85_C  
Document Number: 70252  
S-04031—Rev. D, 04-Jun-01  
www.vishay.com  
8-1  

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