Datasheet > ZL50019GAG2

ZL50019GAG2

更新时间： 2024-02-03 11:15:52

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		电信集成电路
页数	文件大小	规格书
121页	921K
描述
Enhanced 2 K Digital Switch with Stratum 4E DPLL

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ZL50019GAG2 技术参数

生命周期：	Transferred	包装说明：	BGA,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.65	JESD-30 代码：	S-PBGA-B256
JESD-609代码：	e1	长度：	17 mm
功能数量：	1	端子数量：	256
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	SQUARE	封装形式：	GRID ARRAY
认证状态：	Not Qualified	座面最大高度：	1.8 mm
标称供电电压：	1.8 V	表面贴装：	YES
电信集成电路类型：	DIGITAL TIME SWITCH	温度等级：	INDUSTRIAL
端子面层：	TIN SILVER COPPER	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
宽度：	17 mm	Base Number Matches：	1

ZL50019GAG2 数据手册

ZL50019

Data Sheet

Description

The ZL50019 is a maximum 2,048 x 2,048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has

thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and

Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be

independently programmed to operate at any of the following data rates: 2.048, 4.096, 8.192 or 16.384 Mbps. The

ZL50019 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external

tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be configured to operate in

bi-directional mode, in which case STi0 - 31 will be ignored.

The device contains two types of internal memory - data memory and connection memory. There are four modes of

operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the

contents of the connection memory define, for each output stream and channel, the source stream and channel

(the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for

the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be

broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and

status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with

a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 2¹⁵-1 pattern. On the

input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output

channel can be put into a high impedance state.

When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external

20.000 MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input

reference signals (which can be 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz

provided on REF0 - 3). The on-chip DPLL operates in normal, holdover or freerun mode and offers jitter

attenuation. The jitter attenuation function exceeds the Stratum 4E specification.

The configurable non-multiplexed microprocessor port allows users to program various device operating modes

and switching configurations. Users can employ the microprocessor port to perform register read/write, connection

memory read/write and data memory read operations. The port is configurable to interface with either Motorola or

Intel-type microprocessors.

The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.

Zarlink Semiconductor Inc.

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与ZL50019GAG2相关器件

型号	品牌	描述	获取价格	数据表
ZL50019QCC	ZARLINK	Enhanced 2 K Digital Switch with Stratum 4E DPLL	获取价格
ZL50019QCG1	ZARLINK	Enhanced 2 K Digital Switch with Stratum 4E DPLL	获取价格
ZL50020	ZARLINK	Enhanced 2 K Digital Switch	获取价格
ZL50020GAC	MICROSEMI	Digital Time Switch, CMOS, PBGA256, 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256	获取价格
ZL50020GAC	ZARLINK	Enhanced 2 K Digital Switch	获取价格
ZL50020GAG2	ZARLINK	Enhanced 2 K Digital Switch	获取价格

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