Datasheet > ZL50019GAG2

ZL50019GAG2

更新时间： 2024-02-18 16:56:20

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		电信集成电路
页数	文件大小	规格书
121页	921K
描述
Enhanced 2 K Digital Switch with Stratum 4E DPLL

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ZL50019GAG2 技术参数

ZL50019

Data Sheet

•

Per-channel ITU-T G.711 PCM A-Law/µ-Law Translation

Four frame pulse and six reference clock outputs

Three programmable delayed frame pulse outputs

Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz

Input frame pulses: 61 ns, 122 ns, 244 ns

Per-channel constant or variable throughput delay for frame integrity and low latency applications

Per Stream (32) Bit Error Rate Test circuits complying to ITU-O.151

Per-channel high impedance output control

Per-channel message mode

Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses

Connection memory block programming

Supports ST-BUS and GCI-Bus standards for input and output timing

IEEE-1149.1 (JTAG) test port

3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage

Applications

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PBX and IP-PBX

Small and medium digital switching platforms

Remote access servers and concentrators

Wireless base stations and controllers

Multi service access platforms

Digital Loop Carriers

Computer Telephony Integration

Zarlink Semiconductor Inc.

123 4 5 6 7...121

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型号	品牌	描述	获取价格	数据表
ZL50019QCC	ZARLINK	Enhanced 2 K Digital Switch with Stratum 4E DPLL	获取价格
ZL50019QCG1	ZARLINK	Enhanced 2 K Digital Switch with Stratum 4E DPLL	获取价格
ZL50020	ZARLINK	Enhanced 2 K Digital Switch	获取价格
ZL50020GAC	MICROSEMI	Digital Time Switch, CMOS, PBGA256, 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256	获取价格
ZL50020GAC	ZARLINK	Enhanced 2 K Digital Switch	获取价格
ZL50020GAG2	ZARLINK	Enhanced 2 K Digital Switch	获取价格