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ZL50023_06 PDF预览

ZL50023_06

更新时间: 2024-11-25 04:23:27
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关
页数 文件大小 规格书
83页 613K
描述
Enhanced 4 K Digital Switch

ZL50023_06 数据手册

 浏览型号ZL50023_06的Datasheet PDF文件第2页浏览型号ZL50023_06的Datasheet PDF文件第3页浏览型号ZL50023_06的Datasheet PDF文件第4页浏览型号ZL50023_06的Datasheet PDF文件第5页浏览型号ZL50023_06的Datasheet PDF文件第6页浏览型号ZL50023_06的Datasheet PDF文件第7页 
ZL50023  
Enhanced 4 K Digital Switch  
Data Sheet  
January 2006  
Features  
4096 channel x 4096 channel non-blocking digital  
Ordering Information  
Time Division Multiplex (TDM) switch at  
8.192 Mbps and 16.384 Mbps or using a  
combination of ports running at 2.048 Mbps,  
4.096 Mbps, 8.192 Mbps and 16.384 Mbps  
ZL50023GAC  
ZL50023QCC  
256 Ball PBGA Trays  
256 Lead LQFP Trays  
ZL50023GAG2 256 Ball PBGA** Trays, Bake & Drypack  
**Pb Free Tin/Silver/Copper  
32 serial TDM input, 32 serial TDM output  
streams  
-40°C to +85°C  
Output streams can be configured as bi-  
directional for connection to backplanes  
Per-stream output bit and fractional bit  
advancement  
Exceptional input clock cycle to cycle variation  
tolerance (20 ns for all rates)  
Per-channel ITU-T G.711 PCM A-Law/µ-Law  
Translation  
Per-stream input and output data rate conversion  
selection at 2.048 Mbps, 4.096 Mbps 8.192 Mbps  
or 16.384 Mbps. Input and output data rates can  
differ  
Four frame pulse and four reference clock outputs  
Three programmable delayed frame pulse outputs  
Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz  
Input frame pulses: 61 ns, 122 ns, 244 ns  
Per-stream high impedance control outputs  
(STOHZ) for 16 output streams  
Per-channel constant or variable throughput delay  
for frame integrity and low latency applications  
Per-stream input bit delay with flexible sampling  
point selection  
VDD_COREA  
VDD_IOA  
RESET  
VDD_CORE  
VDD_IO  
VSS  
ODE  
P/S Converter  
STio[31:0]  
S/P Converter  
Input Timing  
Data Memory  
STi[31:0]  
FPi  
CKi  
Output HiZ  
Control  
STOHZ[15:0]  
MODE_4M0  
MODE_4M1  
Connection Memory  
FPo[3:0]  
CKo[3:0]  
Output Timing  
FPo_OFF[2:0]  
Internal Registers &  
Microprocessor Interface  
Test Port  
Figure 1 - ZL50023 Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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