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ZL50022_06 PDF预览

ZL50022_06

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关
页数 文件大小 规格书
121页 931K
描述
Enhanced 4 K Digital Switch with Stratum 4E DPLL

ZL50022_06 数据手册

 浏览型号ZL50022_06的Datasheet PDF文件第2页浏览型号ZL50022_06的Datasheet PDF文件第3页浏览型号ZL50022_06的Datasheet PDF文件第4页浏览型号ZL50022_06的Datasheet PDF文件第5页浏览型号ZL50022_06的Datasheet PDF文件第6页浏览型号ZL50022_06的Datasheet PDF文件第7页 
ZL50022  
Enhanced 4 K Digital Switch with  
Stratum 4E DPLL  
Data Sheet  
November 2006  
Features  
4096 channel x 4096 channel non-blocking digital  
Ordering Information  
Time Division Multiplex (TDM) switch at  
8.192 Mbps and 16.384 Mbps or using a  
combination of ports running at 2.048, 4.096,  
8.192 and 16.384 Mbps  
ZL50022GAC  
ZL50022QCC  
ZL50022QCG1  
256 Ball PBGA  
256 Lead LQFP  
256 Lead LQFP*  
Trays  
Trays  
Trays Bake &  
Drypack  
ZL50022GAG2  
256 Ball PBGA**  
Trays, Bake &  
Drypack  
32 serial TDM input, 32 serial TDM output  
streams  
*Pb Free Matte Tin  
**Pb Free Tin/Silver/Copper  
Integrated Digital Phase-Locked Loop (DPLL)  
exceeds Telcordia GR-1244-CORE Stratum 4E  
specifications  
-40°C to +85°C  
Exceptional input clock cycle to cycle variation  
tolerance (20 ns for all rates)  
Output clocks have less than 1 ns of jitter (except  
for the 1.544 MHz output)  
DPLL provides holdover, freerun and jitter  
attenuation features with four independent  
reference source inputs  
Output streams can be configured as bi-  
directional for connection to backplanes  
Per-stream input and output data rate conversion  
selection at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps  
or 16.384 Mbps. Input and output data rates can  
differ  
VDD_COREA  
VDD_IOA  
RESET  
VDD_CORE  
VDD_IO  
VSS  
ODE  
P/S Converter  
STio[31:0]  
S/P Converter  
Input Timing  
Data Memory  
STi[31:0]  
FPi  
CKi  
Output HiZ  
Control  
STOHZ[15:0]  
MODE_4M0  
MODE_4M1  
Connection Memory  
REF0  
REF1  
REF2  
REF3  
FPo[3:0]  
CKo[5:0]  
FPo_OFF[2:0]  
Output Timing  
Test Port  
DPLL  
OSC  
REF_FAIL0  
REF_FAIL1  
REF_FAIL2  
REF_FAIL3  
Internal Registers &  
Microprocessor Interface  
OSC_EN  
Figure 1 - ZL50022 Functional Block Diagram  
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,  
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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