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ZL50021_0611 PDF预览

ZL50021_0611

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关
页数 文件大小 规格书
136页 1013K
描述
Enhanced 4 K Digital Switch with Stratum 3 DPLL

ZL50021_0611 数据手册

 浏览型号ZL50021_0611的Datasheet PDF文件第2页浏览型号ZL50021_0611的Datasheet PDF文件第3页浏览型号ZL50021_0611的Datasheet PDF文件第4页浏览型号ZL50021_0611的Datasheet PDF文件第5页浏览型号ZL50021_0611的Datasheet PDF文件第6页浏览型号ZL50021_0611的Datasheet PDF文件第7页 
ZL50021  
Enhanced 4 K Digital Switch with  
Stratum 3 DPLL  
Data Sheet  
November 2006  
Features  
4096-channel x 4096-channel non-blocking digital  
Ordering Information  
Time Division Multiplex (TDM) switch at 8.192  
and 16.384 Mbps or using a combination of ports  
running at 2.048, 4.096, 8.192 and/or  
16.384 Mbps  
ZL50021GAC  
ZL50021QCC  
ZL50021QCG1  
256 Ball PBGA  
256 Lead LQFP  
256 Lead LQFP*  
Trays  
Trays  
Trays, Bake &  
Drypack  
ZL50021GAG2  
256 Ball PBGA**  
Trays, Bake &  
Drypack  
32 serial TDM input, 32 serial TDM output  
streams  
*Pb Free Matte Tin  
**Pb Free Tin/Silver/Copper  
Integrated Digital Phase-Locked Loop (DPLL)  
exceeds Telcordia GR-1244-CORE Stratum 3  
specifications  
-40°C to +85°C  
Programmable key DPLL parameters (filter corner  
frequency, locking range, auto-holdover  
hysteresis range, phase slope, lock detector  
range)  
Output clocks have less than 1 ns of jitter (except  
for the 1.544 MHz output)  
DPLL provides holdover, freerun and jitter  
attenuation features with four independent  
reference source inputs  
Exceptional input clock cycle to cycle variation  
tolerance (20 ns for all rates)  
Output streams can be configured as bi-  
directional for connection to backplanes  
VDD_COREA  
VDD_IOA  
RESET  
VDD_CORE  
VDD_IO  
VSS  
ODE  
P/S Converter  
STio[31:0]  
S/P Converter  
Input Timing  
Data Memory  
STi[31:0]  
FPi  
CKi  
Output HiZ  
Control  
STOHZ[15:0]  
MODE_4M0  
MODE_4M1  
Connection Memory  
REF0  
REF1  
REF2  
REF3  
FPo[3:0]  
CKo[5:0]  
FPo_OFF[2:0]  
Output Timing  
Test Port  
DPLL  
OSC  
REF_FAIL0  
REF_FAIL1  
REF_FAIL2  
REF_FAIL3  
Internal Registers &  
Microprocessor Interface  
OSC_EN  
Figure 1 - ZL50021 Functional Block Diagram  
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,  
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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