Datasheet > ZL30683LFG7

ZL30683LFG7

更新时间： 2024-11-10 02:50:35

品牌	Logo	应用领域
美高森美 - MICROSEMI		/
页数	文件大小	规格书
6页	360K
描述
1-, 2-, 3-Channel, 10-Input, 18-Output Line Card Timing ICs

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数据手册

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ZL30683LFG7 数据手册

ZL30681, ZL30682, ZL30683

1-, 2-, 3-Channel, 10-Input, 18-Output

Line Card Timing ICs

Product Brief

November 2019

Features

Ordering Information

• One, Two or Three DPLL Channels

• Programmable bandwidth, 14Hz to 470Hz

• Freerun or holdover on loss of all inputs

• Hitless reference switching

ZL30681LFG7 1-Channel 80-lead LGA Trays

ZL30682LFG7 2-Channel 80-lead LGA Trays

ZL30683LFG7 3-Channel 80-lead LGA Trays

NiAu (Pb-free)

Package size: 11 x 11 mm

• High-resolution holdover averaging



-40 C to +85 C

• Per-DPLL phase adjustment, 1ps resolution

• Per-output programmable duty cycle

• Programmable tracking range, phase-slope

limiting, frequency-change limiting and other

advanced features

• Precise output alignment circuitry and per-

output phase adjustment

• Per-output enable/disable and glitchless

• Input Clocks

start/stop (stop high or low)

• Accepts up to 10 differential or CMOS inputs

• Any input frequency from 1kHz to 900MHz

• Per-input activity and frequency monitoring

• Automatic or manual reference switching

• Local Oscillator

• Operates from a single low-cost XO: 23.75-

25MHz, 47.5-50MHz, 114.285-125MHz

• High-stability applications can connect a TCXO

or OCXO (any frequency, any output jitter) to

the OSCI pin to provide a stability reference

• Revertive or nonrevertive switching

• Any input can be a 1PPS SYNC input for

REF+SYNC frequency/phase/time locking

• General Features

• Input-input phase measurement, 1ps resolution

• Input-DPLL phase measurement, 1ps resolution

• Per-input phase adjustment, 1ps resolution

• Automatic self-configuration at power-up from

internal Flash memory

• Input-to-output alignment <200ps (ext feedback)

• Fast REF+SYNC locking for frequency and

• Output Clock Frequency Generation

1PPS phase alignment with lower-cost oscillator

• Any output frequency from <1Hz to 1045MHz

• Internal compensation (1ppt) for local oscillator

(180MHz max for Synth0)

frequency error in DPLLs and input monitors

• High-resolution fractional frequency conversion

• Numerically controlled oscillator behavior in

with 0ppm error

each DPLL and each fractional output divider

• Synthesizers 1 & 2 have integer and fractional

• Easy-to-configure design requires no external

dividers to make a total of 5 frequency families

VCXO or loop filter components

• Output jitter from Synth 1 & 2 is <0.3ps RMS

• 7 GPIO pins with many possible behaviors

• SPI or I²C processor Interface

• Output jitter from fractional dividers is typically

< 1ps RMS, many frequencies <0.5ps RMS

• 1.8V and 3.3V core VDD voltages

• Each HPOUTP/N pair can be LVDS, LVPECL,

HCSL, 2xCMOS, HSTL or programmable diff.

• Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out

• Easy-to-use evaluation/programming software

• In 2xCMOS mode, the P and N pins can be

different frequencies (e.g. 125MHz and 25MHz)

Applications

• Four output banks each with VDDO pin; CMOS

output voltages from 1.5V to 3.3V

•

Line card timing IC for SyncE, SyncE+1588,

SONET/SDH, OTN, wireless base station and

other systems carrier-grade system

• Per-synthesizer phase adjust, 1ps resolution

Microsemi Confidential

12 3 4 5 6

中文翻译

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与ZL30683LFG7相关器件

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