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Z8S18020FEG

更新时间： 2024-09-15 13:01:19
品牌 Logo 应用领域
ZILOG 微处理器
页数 文件大小 规格书
70页 386K
描述
IC 8-BIT, MICROPROCESSOR, PQFP80, QFP-80, Microprocessor

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中文翻译

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Z8S18020FEG 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：QFP,针数：80
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：1.87Samacsys Confidence：4
Samacsys Status：ReleasedSamacsys PartID：828795
Samacsys Pin Count：80Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Quad Flat PackagesSamacsys Footprint Name：80-PIN QFP
Samacsys Released Date：2018-01-10 17:20:01Is Samacsys：N
其他特性：ALSO OPERATES AT 3.3V SUPPLY地址总线宽度：20
位大小：8边界扫描：NO
最大时钟频率：20 MHz外部数据总线宽度：8
格式：FIXED POINT集成缓存：NO
JESD-30 代码：R-PQFP-G80JESD-609代码：e3
长度：20 mm低功率模式：YES
端子数量：80最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：RECTANGULAR
封装形式：FLATPACK峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：3.1 mm
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：14 mm
uPs/uCs/外围集成电路类型：MICROPROCESSORBase Number Matches：1

Z8S18020FEG 数据手册

 浏览型号Z8S18020FEG的Datasheet PDF文件第2页浏览型号Z8S18020FEG的Datasheet PDF文件第3页浏览型号Z8S18020FEG的Datasheet PDF文件第4页浏览型号Z8S18020FEG的Datasheet PDF文件第5页浏览型号Z8S18020FEG的Datasheet PDF文件第6页浏览型号Z8S18020FEG的Datasheet PDF文件第7页 
PRELIMINARY PRODUCT SPECIFICATION  
1
Z80180/Z8S180/  
1
Z8L180 SL1919  
ENHANCED Z180 MICROPROCESSOR  
FEATURES  
®
■ Code Compatible with Zilog Z80 CPU  
■ Two 16-Bit Counter/Timers  
■ Extended Instructions  
■ Two Enhanced UARTs (up to 512 Kbps)  
■ Clock Speeds: 6, 8, 10, 20, 33 MHz  
■ Operating Range: 5V (3.3V@ 20 MHz)  
■ Two Chain-Linked DMA Channels  
■ Low Power-Down Modes  
°
°
■ On-Chip Interrupt Controllers  
■ Three On-Chip Wait-State Generators  
■ On-Chip Oscillator/Generator  
■ Expanded MMU Addressing (up to 1 MB)  
■ Clocked Serial I/O Port  
■ Operating Temperature Range: 0 C to +70 C  
°
°
■ -40 C to +85 C Extended Temperature Range  
■ Three Packaging Styles  
–
–
–
68-Pin PLCC  
64-Pin DIP  
80-Pin QFP  
GENERAL DESCRIPTION  
™
The enhanced Z80180/Z8S180/Z8L180 significantly im-  
Not only does the Z80180/Z8S180/Z8L180 consume less  
power during normal operations than the previous model,  
it has also been designed with three modes intended to fur-  
proves on the previous Z80180 models while still providing  
full backward compatibility with existing Zilog Z80 devices.  
The Z80180/Z8S180/Z8L180 now offers faster execution  
speeds, power saving modes, and EMI noise reduction.  
ther reduce the power consumption. Zilog reduced I pow-  
cc  
er consumption during STANDBY Mode to a minimum of  
10 µA by stopping the external oscillators and internal  
clock. The SLEEP mode reduces power by placing the  
CPU into a “stopped” state, thereby consuming less cur-  
rent while the on-chip I/O device is still operating. The  
SYSTEM STOP mode places both the CPU and the on-  
chip peripherals into a “stopped” mode, thereby reducing  
power consumption even further.  
This enhanced Z180 design also incorporates additional  
feature enhancements to the ASCIs, DMAs, and I  
cc  
STANDBY Mode power consumption. With the addition of  
“ESCC-like” Baud Rate Generators (BRGs), the two ASCIs  
now have the flexibility and capability to transfer data asyn-  
chronously at rates of up to 512 Kbps. In addition, the ASCI  
receiver has added a 4-byte First In First Out (FIFO) which  
can be used to buffer incoming data to reduce the inci-  
dence of overrun errors. The DMAs have been modified to  
allow for a “chain-linking” of the two DMA channels when  
set to take their DMA requests from the same peripherals  
device. This feature allows for non-stop DMA operation be-  
tween the two DMA channels, reducing the amount of CPU  
intervention (Figure 1).  
A new clock doubler feature has been implemented in the  
Z80180/Z8S180/Z8L180 device that allows the program-  
mer to double the internal clock from that of the external  
clock. This provides a systems cost savings by allowing  
the use of lower cost, lower frequency crystals instead of  
the higher cost, and higher speed oscillators.  
The Enhanced Z180 is housed in 80-pin QFP, 68-pin  
PLCC, and 64-pin DIP packages.  
DS971800401  
P R E L I M I N A R Y  
1-1  
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