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Z8S18020FSG

更新时间： 2024-11-05 14:12:43
品牌 Logo 应用领域
IXYS 时钟外围集成电路
页数 文件大小 规格书
71页 910K
描述
Microprocessor, 8-Bit, 20MHz, CMOS, PQFP80, QFP-80

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中文翻译

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Z8S18020FSG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：QFP,针数：80
Reach Compliance Code：compliantECCN代码：3A001.A.2.C
HTS代码：8542.31.00.01风险等级：5.41
其他特性：ALSO OPERATES AT 3.3V SUPPLY地址总线宽度：20
位大小：8边界扫描：NO
最大时钟频率：20 MHz外部数据总线宽度：8
格式：FIXED POINT集成缓存：NO
JESD-30 代码：R-PQFP-G80JESD-609代码：e3
长度：20 mm低功率模式：YES
端子数量：80最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装形状：RECTANGULAR
封装形式：FLATPACK峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：3.1 mm
速度：20 MHz最大压摆率：120 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：14 mm
uPs/uCs/外围集成电路类型：MICROPROCESSORBase Number Matches：1

Z8S18020FSG 数据手册

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Code Compatible with ZiLOG Z80 CPU  
Extended Instructions  
Two 16-Bit Counter/Timers  
Two Enhanced UARTs (up to 512 Kbps)  
Clock Speeds: 10, 20, 33 MHz  
Two Chain-Linked DMA Channels  
Low Power-Down Modes  
Operating Range: 5V (3.3V@ 20 MHz)  
Operating Temperature Range: 0°C to +70°C  
–40°C to +85°C Extended Temperature Range  
Three Packaging Styles  
On-Chip Interrupt Controllers  
Three On-Chip Wait-State Generators  
On-Chip Oscillator/Generator  
Expanded MMU Addressing (Up to 1 MB)  
Clocked Serial I/O Port  
–
–
–
68-Pin PLCC  
64-Pin DIP  
80-Pin QFP  
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™
three modes intended to further reduce power consumption.  
Power consumption during 56#0&$; Mode is reduced to  
10 µA by stopping the external oscillators and internal  
clock. The 5.''2 mode reduces power by placing the CPU  
into a stopped state, consuming less current while the on-  
chip I/O devices still operate. The 5;56'/ꢅ5612 mode  
places both the CPU and the on-chip peripherals into a  
stopped mode, reducing power consumption even further.  
The enhanced Z8S180/Z8L180 significantly improves on  
previous Z80180 models, while still providing full back-  
ward compatibility with existing ZiLOG Z80 devices. The  
Z8S180/Z8L180 now offers faster execution speeds, pow-  
er-saving modes, and EMI noise reduction.  
™
This enhanced Z180 design also incorporates additional  
feature enhancements to the ASCIs, DMAs, and 56#0&$;  
mode power consumption. With the addition of ESCC-like  
BaudRateGenerators(BRGs),thetwoASCIsoffertheflex-  
ibility and capability to transfer data asynchronously atrates  
of up to 512 Kbps. In addition, the ASCI receiver features  
a 4-byte first in/first out (FIFO) buffer which reduces the  
likelihoodofoverrunerrors.TheDMAshavebeenmodified  
to allow for chain-linking of the two DMA channels when  
set to take their DMA requests from the same peripherals  
device. This feature allows for nonstop DMA operation be-  
tween the two DMA channels.  
A new clock-doubler feature in the Z8S180/Z8L180 allows  
the internal clock speed to be twice the external clock speed.  
As a result, system cost is reduced by allowing the use of  
lower-cost, lower-frequency crystals.  
The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC,  
and 64-pin DIP packages.  
0QVGꢅ All Signals with an overline are active Low. For exam-  
ple: B/W, in which WORD is active Low; or B/W, in  
which BYTE is active Low.  
NotonlydoestheZ8S180/Z8L180consumelesspowerdur-  
ing normal operations than the previous model, it offers  
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中文翻译

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