Datasheet > Z8S18033FEG

Z8S18033FEG

更新时间： 2024-11-07 09:30:43

品牌	Logo	应用领域
IXYS		时钟外围集成电路
页数	文件大小	规格书
71页	531K
描述
IC 8-BIT, MICROPROCESSOR, PQFP80, QFP-80, Microprocessor

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

Z8S18033FEG 数据手册

24'.+/+0#4;ꢀ241&7%6ꢀ52'%+(+%#6+10

<ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂ

'0*#0%'&ꢅ<ꢄꢆꢀꢅ/+%41241%'5514

1(('45ꢅ(#56'4ꢅ':'%76+10ꢇ

219'4ꢃ5#8'4ꢅ/1&'ꢇꢅ.19ꢅ'/+

('#674'5

Code Compatible with ZiLOG Z80 CPU

Extended Instructions

Two 16-Bit Counter/Timers

Two Enhanced UARTs (up to 512 Kbps)

Clock Speeds: 10, 20, 33 MHz

Two Chain-Linked DMA Channels

Low Power-Down Modes

Operating Range: 5V (3.3V@ 20 MHz)

Operating Temperature Range: 0°C to +70°C

–40°C to +85°C Extended Temperature Range

Three Packaging Styles

On-Chip Interrupt Controllers

Three On-Chip Wait-State Generators

On-Chip Oscillator/Generator

Expanded MMU Addressing (Up to 1 MB)

Clocked Serial I/O Port

–

68-Pin PLCC

64-Pin DIP

80-Pin QFP

)'0'4#.ꢄ&'5%4+26+10

™

three modes intended to further reduce power consumption.

Power consumption during 56#0&$; Mode is reduced to

10 µA by stopping the external oscillators and internal

clock. The 5.''2 mode reduces power by placing the CPU

into a stopped state, consuming less current while the on-

chip I/O devices still operate. The 5;56'/ꢅ5612 mode

places both the CPU and the on-chip peripherals into a

stopped mode, reducing power consumption even further.

The enhanced Z8S180/Z8L180 significantly improves on

previous Z80180 models, while still providing full back-

ward compatibility with existing ZiLOG Z80 devices. The

Z8S180/Z8L180 now offers faster execution speeds, pow-

er-saving modes, and EMI noise reduction.

™

This enhanced Z180 design also incorporates additional

feature enhancements to the ASCIs, DMAs, and 56#0&$;

mode power consumption. With the addition of ESCC-like

BaudRateGenerators(BRGs),thetwoASCIsoffertheflex-

ibility and capability to transfer data asynchronously atrates

of up to 512 Kbps. In addition, the ASCI receiver features

a 4-byte first in/first out (FIFO) buffer which reduces the

likelihoodofoverrunerrors.TheDMAshavebeenmodified

to allow for chain-linking of the two DMA channels when

set to take their DMA requests from the same peripherals

device. This feature allows for nonstop DMA operation be-

tween the two DMA channels.

A new clock-doubler feature in the Z8S180/Z8L180 allows

the internal clock speed to be twice the external clock speed.

As a result, system cost is reduced by allowing the use of

lower-cost, lower-frequency crystals.

The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC,

and 64-pin DIP packages.

0QVGꢅ All Signals with an overline are active Low. For exam-

ple: B/W, in which WORD is active Low; or B/W, in

which BYTE is active Low.

NotonlydoestheZ8S180/Z8L180consumelesspowerdur-

ing normal operations than the previous model, it offers

&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ

ꢄ

12 3 4 5 6 7...71

中文翻译

下载PDF

与Z8S18033FEG相关器件

型号	品牌	获取价格	描述	数据表
Z8S18033FSC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18033FSG	IXYS	获取价格	IC 33 MHz, 8-BIT, MICROPROCESSOR, PQFP80, QFP-80, Microprocessor
Z8S18033PEC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18033PSC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18033VEC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18033VEG	ZILOG	获取价格	IC 33 MHz, 8-BIT, MICROPROCESSOR, PQCC68, PLASTIC, LCC-68, Microprocessor
Z8S18033VSC	ZILOG	获取价格	ENHANCED Z180 MICROPROCESSOR
Z8S18033VSG	IXYS	获取价格	Microprocessor, 8-Bit, 33MHz, CMOS, PQCC68, PLASTIC, LCC-68
Z8W27V	KEC	获取价格	DO-218
Z8W37V	KEC	获取价格	DO-218

与Z8S18033FEG相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

12
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

33

产品中心

服务支持

精选活动

关于我们

帮助中心

Z8S18033FEG

Z8S18033FEG 数据手册

与Z8S18033FEG相关器件

与Z8S18033FEG相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

Z8S18033FEG

Z8S18033FEG 数据手册

与Z8S18033FEG相关器件

与Z8S18033FEG相关文章

您还可以找

您在本页遇到什么问题？