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Z16C3010ASG PDF预览

Z16C3010ASG

更新时间: 2024-11-01 20:29:35
品牌 Logo 应用领域
IXYS 通信时钟数据传输外围集成电路
页数 文件大小 规格书
87页 1040K
描述
Multi Protocol Controller, 2 Channel(s), 1.25MBps, CMOS, PQFP100, VQFP-100

Z16C3010ASG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:not_compliantHTS代码:8542.31.00.01
风险等级:5.62Is Samacsys:N
地址总线宽度:16边界扫描:NO
总线兼容性:8X86; 680X0最大时钟频率:20 MHz
通信协议:ASYNC, BIT; SYNC, BYTE; SYNC, HDLC; SYNC, SDLC; BISYNC; EXT SYNC; BISYNC TRANSPARENT; NBIP数据编码/解码方法:NRZ; NRZI-MARK; NRZI-SPACE; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER); DIFF BIPH-LEVEL
最大数据传输速率:1.25 MBps外部数据总线宽度:16
JESD-30 代码:S-PQFP-G100长度:14 mm
低功率模式:NO串行 I/O 数:2
端子数量:100最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, MULTI PROTOCOL
Base Number Matches:1

Z16C3010ASG 数据手册

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PRODUCT SPECIFICATION  
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Two Independent 0-to-10-mbps Full-Duplex Channels,  
each with Two Baud Rate Generators and One Digital  
Phase-Locked Loop for Clock Recovery  
Receive Sync Stripping; Optional Preamble Transmis-  
sion; 16- or 32-Bit CRC  
Transparent Bisync Mode with EBCDIC or ASCII Char-  
acter Code; Automatic CRC Handling; Programmable  
Idle Line Condition; Optional Preamble Transmission;  
Automatic Recognition of DLE, SYN, SOH, ITX, ETX,  
ETB, EOT, ENQ and ITB  
32-Byte Data FIFO’s for each Receiver and Transmitter  
110-ns Bus Cycle Time, 16-Bit Data Bus Bandwidth  
Multi-Protocol Operation under Program Control with  
External Character Sync Mode for Receive  
Independent Mode Selection for Receiver and Transmit-  
ter  
HDLC/SDLC Mode with Eight-Bit Address Compare;  
Extended Address Field Option; 16- or 32-Bit CRC; Pro-  
grammable Idle Line Condition; Optional Preamble  
Transmission and Loop Mode  
Async Mode with 1 to 8 Bits/Character, 1/16 to 2 Stop  
Bits/Character in 1/16-Bit Increments; Programmable  
Clock Factor; Break Detect and Generation; Odd, Even,  
Mark, Space or no Parity and Framing Error Detection;  
Supports One Address/Data Bit and MIL STD 1553B  
Protocols  
DMA Interface with Separate Request and Acknowl-  
edge for Each Receiver and Transmitter  
Channel Load Command for DMA Controlled Initializa-  
tion  
Byte Oriented Synchronous Mode with One to Eight  
Bits/Character; Programmable Idle Line Condition; Op-  
tional Receive Sync Stripping; Optional Preamble  
Transmission; 16- or 32-Bit CRC and Transmit-to-Re-  
ceive Slaving (for X.21)  
Flexible Bus Interface for Direct Connection to Most  
Microprocessors; User Programmable for 8 or 16 Bits  
Wide. Directly Supports 680X0 Family or 8X86 Family  
Bus Interfaces  
Low Power CMOS  
Bisync Mode with 2- to 16-Bit Programmable Sync  
Character; Programmable Idle Line Condition; Optional 68-Pin PLCC/100-Pin VQFP Packages  
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The Z16C30 USC™ Universal Serial Controller is a dual-  
channel multi-protocol data communications peripheral de-  
signed for use with any conventional multiplexed or non-  
multiplexed bus. The USC functions as a serial-to-parallel,  
parallel-to-serial converter/controller and may be software  
configured to satisfy a wide variety of serial communica-  
tions applications. The device contains a variety of new, so-  
phisticated internal functions including two baud rate gen-  
erators per channel, one digital phase-locked loop per  
channel, character counters for both receive and transmit in  
each channel and 32-byte data FIFO’s for each receiver and  
transmitter (Figure 1).  
ZiLOG now offers a high speed version of the USC with  
improved bus bandwidth. CPU bus accesses have been  
shortened from 160 ns per access to 110 ns per access. The  
USC has a transmit and receive clock range of up to 10 MHz  
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