Datasheet > Z16C3220VSG1660

Z16C3220VSG1660

更新时间： 2024-02-15 09:30:45

品牌	Logo	应用领域
ZILOG		/
页数	文件大小	规格书
122页	520K
描述
IC CONTROLLER 20MHZ CMOS 68PLCC

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中文翻译

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数据手册

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Z16C3220VSG1660 数据手册

Z16C32 IUSC^™

P R E L I M I N A R Y

ILOG

PRELIMINARY PRODUCT SPECIFICATION

Z16C32

IUSC^™INTEGRATED UNIVERSAL

SERIAL CONTROLLER

FEATURES

■

Two Full-Capacity 20 MHz DMA Channels, Each with

32-Bit Addressing and 16-Bit Data Transfers.

■

HDLC/SDLC Mode with 8-Bit Address Compare;

Extended Address Field Option; 16- or 32-Bit CRC;

Programmable Idle Line Condition;OptionalPreamble

Transmission and Loop Mode. Selectable Number of

Flags Between Back-to-Back Frames.

DMA Modes Include Single Buffer, Pipelined, Array-

Chained and Linked-Array Chained.

Ring BufferFeature Supports CircularQueue ofBuffers

in Memory.

■

Byte Oriented Synchronous Mode with One-to-Eight

Bits/Character; Programmable Sync and Idle Line

Conditions;OptionalReceive Sync Stripping;Optional

Preamble Transmission; 16- or 32-Bit CRC; Transmit-

to-Receive Slaving (for X.21).

Linked Frame Status Transfer Feature Writes Status

Information for Received Frames and Reads Control

Information for Transmit Frames to the DMA Channel’s

ArrayorLinked Listto SignificantlySimplifyProcessing

Frame Status and Control Information.

■

External Character Sync Mode for Receive

Transparent Bisync Mode with EBCDIC or ASCII

Cha ra c te r Cod e ; Automa tic CRC Ha nd ling ;

Programmable Idle Line Condition;OptionalPreamble

Transmission; Automatic Recognition of DLE, SYN,

SOH, ITX, ETX, ETB, EOT, ENQ and ITB.

■

Programmable Throttling of DMA Bus Occupancy in

Burst Mode with Bus Occupancy Time Limitation.

0 to 20 Mbit/sec, Full-Duplex Channel, with Two Baud

Rate Generators and a Digital Phase-Locked Loop for

Clock Recovery.

■

Flexible Bus Interface for Direct Connection to Most

Microprocessors; User Programmable for 8 or 16 Bits

Wide. Directly Supports 680X0 Family or 8X86 Family

Bus Interfaces.

■

32-Byte Data FIFOs for Receiver and Transmitter

Up to 12.5 MByte/sec (16-Bit) Data Bus Bandwidth

Receive and Transmit Time Slot Assigners for ISDN,

T1 and E1 (CEPT) Applications.

Multiprotocol Operation Under Program Control with

Independent Mode Selection for Receiver and

Transmitter.

■

8-Bit General-Purpose Port with Transition Detection

Low Power CMOS

■

Async Mode with One-to-Eight Bits/Character, 1/16 to

Two Stop Bits/Character in 1/16 Bit Increments; 16x,

32x, or 64x Ove rs a mp ling ; Bre a k De te c t a nd

Generation; Odd, Even, Mark, Space or No Parity and

Framing Error Detection. Supports 9-Bit and MIL-STD-

1553B Protocols.

68-Pin PLCC Package

Electronic Programmer's Manual Support Tool and

Software Drivers are Available.

GENERAL DESCRIPTION

The Z16C32 IUSC^™(Integrated UniversalSerialController)

is a multiprotocol datacommunications device with on-

chip dual-channel DMA. The integration of a high-speed

serial communications channel with high-performance

DMA facilitates higher data throughput than can be

achieved with discrete serial/DMA chip combinations.

PS97USC0200

12 3 4 5 6 7...122

中文翻译

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与Z16C3220VSG1660相关器件

型号	品牌	获取价格	描述	数据表
Z16C32FSC1660	ETC	获取价格	Communications Controller
Z16C32IUSC	ZILOG	获取价格	IUSC? INTEGRATED UNIVERSAL SERIAL CONTROLLER
Z16C32SL	ZILOG	获取价格	IUSC⑩ INTEGRATED UNIVERSAL SERIAL CONTROLLER
Z16C32SL1660	ZILOG	获取价格	IUSC⑩ INTEGRATED UNIVERSAL SERIAL CONTROLLER
Z16C32VSC1660	ETC	获取价格	Communications Controller
Z16C35	ZILOG	获取价格	CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER
Z16C3510FEC	ZILOG	获取价格	CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER
Z16C3510FED	ZILOG	获取价格	CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER
Z16C3510FEE	ZILOG	获取价格	CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER
Z16C3510FSC	ZILOG	获取价格	CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER

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