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Z16C3220VSG PDF预览

Z16C3220VSG

更新时间： 2024-09-27 15:58:47
品牌 Logo 应用领域
IXYS 通信时钟数据传输外围集成电路
页数 文件大小 规格书
122页 520K
描述
Multi Protocol Controller, 1 Channel(s), 2.5MBps, CMOS, PQCC68, LCC-68

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中文翻译

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Z16C3220VSG 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：QCCJ, LDCC68,1.0SQReach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.76
地址总线宽度：16边界扫描：NO
最大时钟频率：20 MHz通信协议：ASYNC, BIT; SYNC, BYTE; SYNC, HDLC; SYNC, SDLC; BISYNC; EXT SYNC; BISYNC TRANSPARENT; NBIP
数据编码/解码方法：NRZ; NRZB; NRZI-MARK; NRZI-SPACE; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)最大数据传输速率：2.5 MBps
外部数据总线宽度：16JESD-30 代码：S-PQCC-J68
长度：24.23 mm低功率模式：NO
串行 I/O 数：1端子数量：68
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC68,1.0SQ封装形状：SQUARE
封装形式：CHIP CARRIER电源：5 V
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Other uPs/uCs/Peripheral ICs最大压摆率：50 mA
最大供电电压：5.5 V最小供电电压：4.5 V
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD宽度：24.23 mm
uPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, MULTI PROTOCOLBase Number Matches：1

Z16C3220VSG 数据手册

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Z16C32 IUSC
Z
ILOG  
PRELIMINARY PRODUCT SPECIFICATION  
Z16C32  
IUSC™ INTEGRATED UNIVERSAL  
SERIAL CONTROLLER  
FEATURES  
■
■
■
■
Two Full-Capacity 20 MHz DMA Channels, Each with  
32-Bit Addressing and 16-Bit Data Transfers.  
■
HDLC/SDLC Mode with 8-Bit Address Compare;  
Extended Address Field Option; 16- or 32-Bit CRC;  
Programmable Idle Line Condition;OptionalPreamble  
Transmission and Loop Mode. Selectable Number of  
Flags Between Back-to-Back Frames.  
DMA Modes Include Single Buffer, Pipelined, Array-  
Chained and Linked-Array Chained.  
Ring BufferFeature Supports CircularQueue ofBuffers  
in Memory.  
■
Byte Oriented Synchronous Mode with One-to-Eight  
Bits/Character; Programmable Sync and Idle Line  
Conditions;OptionalReceive Sync Stripping;Optional  
Preamble Transmission; 16- or 32-Bit CRC; Transmit-  
to-Receive Slaving (for X.21).  
Linked Frame Status Transfer Feature Writes Status  
Information for Received Frames and Reads Control  
Information for Transmit Frames to the DMA Channel’s  
ArrayorLinked Listto SignificantlySimplifyProcessing  
Frame Status and Control Information.  
■
■
External Character Sync Mode for Receive  
Transparent Bisync Mode with EBCDIC or ASCII  
Cha ra c te r Cod e ; Automa tic CRC Ha nd ling ;  
Programmable Idle Line Condition;OptionalPreamble  
Transmission; Automatic Recognition of DLE, SYN,  
SOH, ITX, ETX, ETB, EOT, ENQ and ITB.  
■
■
Programmable Throttling of DMA Bus Occupancy in  
Burst Mode with Bus Occupancy Time Limitation.  
0 to 20 Mbit/sec, Full-Duplex Channel, with Two Baud  
Rate Generators and a Digital Phase-Locked Loop for  
Clock Recovery.  
■
■
Flexible Bus Interface for Direct Connection to Most  
Microprocessors; User Programmable for 8 or 16 Bits  
Wide. Directly Supports 680X0 Family or 8X86 Family  
Bus Interfaces.  
■
■
■
32-Byte Data FIFOs for Receiver and Transmitter  
Up to 12.5 MByte/sec (16-Bit) Data Bus Bandwidth  
Receive and Transmit Time Slot Assigners for ISDN,  
T1 and E1 (CEPT) Applications.  
Multiprotocol Operation Under Program Control with  
Independent Mode Selection for Receiver and  
Transmitter.  
■
■
■
■
8-Bit General-Purpose Port with Transition Detection  
Low Power CMOS  
■
Async Mode with One-to-Eight Bits/Character, 1/16 to  
Two Stop Bits/Character in 1/16 Bit Increments; 16x,  
32x, or 64x Ove rs a mp ling ; Bre a k De te c t a nd  
Generation; Odd, Even, Mark, Space or No Parity and  
Framing Error Detection. Supports 9-Bit and MIL-STD-  
1553B Protocols.  
68-Pin PLCC Package  
Electronic Programmer's Manual Support Tool and  
Software Drivers are Available.  
GENERAL DESCRIPTION  
The Z16C32 IUSC™ (Integrated UniversalSerialController)  
is a multiprotocol datacommunications device with on-  
chip dual-channel DMA. The integration of a high-speed  
serial communications channel with high-performance  
DMA facilitates higher data throughput than can be  
achieved with discrete serial/DMA chip combinations.  
1
PS97USC0200  
1234567...122

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