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XRT86VX38IB329 PDF预览

XRT86VX38IB329

更新时间: 2024-02-26 16:44:25
品牌 Logo 应用领域
艾科嘉 - EXAR 数字传输控制器电信集成电路电信电路
页数 文件大小 规格书
200页 1366K
描述
8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

XRT86VX38IB329 技术参数

是否Rohs认证:不符合生命周期:Active
包装说明:FBGA,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.28
Is Samacsys:NJESD-30 代码:S-PBGA-B329
长度:17 mm湿度敏感等级:1
功能数量:1端子数量:329
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装形状:SQUARE封装形式:GRID ARRAY, FINE PITCH
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:1.71 mm标称供电电压:1.8 V
表面贴装:YES技术:CMOS
电信集成电路类型:FRAMER温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:17 mmBase Number Matches:1

XRT86VX38IB329 数据手册

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XRT86VX38  
8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION  
2009  
REV. 1.0.1  
from the incoming T1/E1/J1 data stream and write the  
GENERAL DESCRIPTION  
contents into the Receive HDLC buffers. Each framer  
also contains a Transmit and Overhead Data Input  
port, which permits Data Link Terminal Equipment  
direct access to the outbound T1/E1/J1 frames.  
Likewise, a Receive Overhead output data port  
permits Data Link Terminal Equipment direct access  
to the Data Link bits of the inbound T1/E1/J1 frames.  
The XRT86VX38 is an eight-channel 1.544 Mbit/s or  
2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Short-  
3
hual LIU integrated solution featuring R technology  
(Relayless, Reconfigurable, Redundancy) and BITS  
Timing element. The physical interface is optimized  
with internal impedance, and with the patented pad  
structure, the XRT86VX38 provides protection from  
power failures and hot swapping.  
The XRT86VX38 fully meets all of the latest T1/E1/J1  
specifications:  
ANSI T1/E1.107-1988, ANSI T1/  
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/  
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and  
ITU G-703, G.704, G706 and G.733, AT&T Pub.  
43801, and ETS 300 011, 300 233, JT G.703, JT  
G.704, JT G706, I.431. Extensive test and diagnostic  
functions include Loop-backs, Boundary scan,  
Pseudo Random bit sequence (PRBS) test pattern  
generation, Performance Monitor, Bit Error Rate  
(BER) meter, forced error insertion, and LAPD  
unchannelized data payload processing according to  
ITU-T standard Q.921.  
The XRT86VX38 contains an integrated DS1/E1/J1  
framer and LIU which provide DS1/E1/J1 framing and  
error accumulation in accordance with ANSI/ITU_T  
specifications. Each framer has its own framing  
synchronizer and transmit-receive slip buffers. The  
slip buffers can be independently enabled or disabled  
as required and can be configured to frame to the  
common DS1/E1/J1 signal formats.  
Each Framer block contains its own Transmit and  
Receive T1/E1/J1 Framing function. There are 3  
Transmit HDLC controllers per channel which  
encapsulate contents of the Transmit HDLC buffers  
into LAPD Message frames. There are 3 Receive  
HDLC controllers per channel which extract the  
payload content of Receive LAPD Message frames  
.
APPLICATIONS AND FEATURES (NEXT PAGE)  
FIGURE 1. XRT86VX38 EIGHT CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO  
External Data  
Link Controller  
Local PCM  
Tx Overhead In  
Rx Overhead Out  
Highway  
XRT86VX38  
1:2 Turns Ratio  
1:1 Turns Ratio  
TTIP  
2-Frame  
Slip Buffer  
Elastic Store  
Tx Serial  
Data In  
Tx LIU  
Interface  
Tx Framer  
Rx Framer  
TRING  
Tx Serial  
Clock  
LLB  
LB  
RTIP  
2-Frame  
Slip Buffer  
Elastic Store  
Rx Serial  
Data Out  
Rx LIU  
Interface  
RRING  
Rx Serial  
Clock  
LIU &  
Loopback  
Control  
PRBS  
Generator &  
Analyser  
HDLC/LAPD  
Controllers  
Performance  
Monitor  
RxLOS  
Line Side  
8kHz sync  
OSC  
DMA  
Interface  
Microprocessor  
Interface  
Signaling &  
Alarms  
JTAG  
Back Plane  
1.544-16.384 Mbit/s  
WR  
ALE_AS  
RD  
4
3
P  
A[11:0]  
INT  
System (Terminal) Side  
D[7:0]  
Select  
RDY_DTACK  
TxON  
Intel/Motorola µP  
Configuration, Control &  
Status Monitor  
Memory  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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