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XR16V2552IJTR-F PDF预览

XR16V2552IJTR-F

更新时间: 2024-11-22 21:12:11
品牌 Logo 应用领域
艾科嘉 - EXAR 外围集成电路
页数 文件大小 规格书
46页 1016K
描述
Serial I/O Controller, CMOS, PQCC44

XR16V2552IJTR-F 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QCCJ, LDCC44,.7SQReach Compliance Code:compliant
风险等级:5.84JESD-30 代码:S-PQCC-J44
JESD-609代码:e3端子数量:44
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC44,.7SQ封装形状:SQUARE
封装形式:CHIP CARRIER电源:2.5/3.3 V
认证状态:Not Qualified子类别:Serial IO/Communication Controllers
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUADuPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

XR16V2552IJTR-F 数据手册

 浏览型号XR16V2552IJTR-F的Datasheet PDF文件第2页浏览型号XR16V2552IJTR-F的Datasheet PDF文件第3页浏览型号XR16V2552IJTR-F的Datasheet PDF文件第4页浏览型号XR16V2552IJTR-F的Datasheet PDF文件第5页浏览型号XR16V2552IJTR-F的Datasheet PDF文件第6页浏览型号XR16V2552IJTR-F的Datasheet PDF文件第7页 
XR16V2552  
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO  
MARCH 2010  
REV. 1.0.3  
FEATURES  
GENERAL DESCRIPTION  
2.25 to 3.6 Volt Operation  
5 Volt Tolerant Inputs  
1
The XR16V2552 (V2552) is a high performance dual  
universal asynchronous receiver and transmitter  
(UART) with 16 byte TX and RX FIFOs. The device  
operates from 2.25 to 3.6 volts with 5 Volt tolerant  
inputs and is pin-to-pin compatible to Exar’s  
ST16C2552 and XR16L2552. The V2552 register set  
is compatible to the ST16C2552 and the XR16L2552.  
It supports the Exar’s enhanced features of  
selectable FIFO trigger level, automatic hardware  
(RTS/CTS) and software (Xon/Xoff) flow control, and  
a complete modem interface. Onboard registers  
provide the user with operational status and data  
error flags. An internal loopback capability allows  
system diagnostics. Independent programmable  
baud rate generators are provided in each channel to  
select data rates up to 16 Mbps at 3.3 Volt with 4X  
sampling clock. The V2552 is available in 44-pin  
PLCC and 32-pin QFN packages.  
Pin-to-pin compatible to Exar’s XR16L2552 in the  
44-PLCC package  
Two independent UART channels  
Register set identical to 16V2550  
Data rate of up to 16 Mbps at 3.3 V, and  
12.5 Mbps at 2.5 V with 4X sampling rate  
Fractional Baud Rate Generator  
Transmit and Receive FIFOs of 16 bytes  
Selectable TX and RX FIFO Trigger Levels  
Automatic Hardware (RTS/CTS) Flow Control  
Automatic Software (Xon/Xoff) Flow Control  
Wireless Infrared (IrDA 1.0) Encoder/Decoder  
Automatic sleep mode  
NOTE: 1 Covered by U.S. Patent #5,649,122  
Full modem interface  
APPLICATIONS  
Alternate Function Register  
Portable Appliances  
Device Identification and Revision  
Telecommunication Network Routers  
Ethernet Network Routers  
Crystal oscillator (up to 32MHz) or external clock  
(up to 64MHz) input  
44-PLCC and 32-QFN packages  
Cellular Data Devices  
Factory Automation and Process Controls  
FIGURE 1. XR16V2552 BLOCK DIAGRAM  
* 5 Volt Tolerant Inputs  
2.25 to 3.6 Volt VCC  
A2:A0  
D7:D0  
GND  
IOR#  
IOW#  
UART Channel A  
TXA, RXA, DTRA#,  
16 Byte TX FIFO  
CS#  
UART  
DSRA#, RTSA#,  
DTSA#, CDA#, RIA#,  
OP2A#  
Regs  
IR  
ENDEC  
CHSEL  
TX & RX  
8-bit Data  
Bus  
Interface  
INTA  
INTB  
BRG  
16 Byte RX FIFO  
TXRDYA#  
TXRDYB#  
RXRDYA#  
RXRDYB#  
TXB, RXB, DTRB#,  
DSRB#, RTSB#,  
CTSB#, CDB#, RIB#,  
OP2B#  
UART Channel B  
(same as Channel A)  
Reset  
XTAL1  
XTAL2  
Crystal Osc/Buffer  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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