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XR16V2652IL32 PDF预览

XR16V2652IL32

更新时间: 2024-11-22 02:56:59
品牌 Logo 应用领域
艾科嘉 - EXAR 先进先出芯片
页数 文件大小 规格书
48页 1012K
描述
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO

XR16V2652IL32 数据手册

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PRELIMINARY  
XR16V2652  
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO  
JUNE 2006  
REV. P1.0.0  
FEATURES  
GENERAL DESCRIPTION  
2.25 to 3.6 Volt Operation  
5 Volt Tolerant Inputs  
1
The XR16V2652 (V2652) is a high performance dual  
universal asynchronous receiver and transmitter  
(UART) with 32 byte TX and RX FIFOs. The device  
operates from 2.25 to 3.6 volts with 5 Volt tolerant  
inputs and is pin-to-pin compatible to Exar’s  
Pin-to-pin compatible to Exar’s XR16V2752 in the  
44-PLCC package  
ST16C2552,  
XR16L2552,  
XR16V2552  
and  
Two independent UART channels  
XR16L2752. The V2652 register set is compatible to  
the ST16C2552 and the XR16V2552. It supports the  
Exar’s enhanced features of selectable FIFO trigger  
level, automatic hardware (RTS/CTS) and software  
flow control and a complete modem interface.  
Onboard registers provide the user with operational  
status and data error flags. An internal loopback  
capability allows system diagnostics. Independent  
programmable baud rate generators are provided in  
each channel to select data rates up to 16 Mbps at  
3.3 Volt with 4X sampling clock. The V2652 is  
available in 44-pin PLCC and 32-pin QFN packages.  
Register set compatible to ST16C2552  
Data rate of up to 16 Mbps at 3.3 V and  
12.5 Mbps at 2.5 V with 4X sampling rate  
Fractional Baud Rate Generator  
Transmit and Receive FIFOs of 32 bytes  
Selectable TX and RX FIFO Trigger Levels  
Automatic Hardware (RTS/CTS) Flow Control  
Automatic Software (Xon/Xoff) Flow Control  
Wireless Infrared (IrDA 1.0) Encoder/Decoder  
Automatic sleep mode  
NOTE: 1 Covered by U.S. Patent #5,649,122  
Full modem interface  
APPLICATIONS  
Alternate Function Register  
Portable Appliances  
Telecommunication Network Routers  
Ethernet Network Routers  
Cellular Data Devices  
Factory Automation and Process Controls  
Device Identification and Revision  
Crystal oscillator or external clock input  
Crystal oscillator (up to 32 MHz) or external clock  
(up to 64 MHz) input  
44-PLCC and 32-QFN packages  
FIGURE 1. XR16V2652 BLOCK DIAGRAM  
* 5 Volt Tolerant Inputs  
2.25 to 3.6 Volt VCC  
A2:A0  
D7:D0  
GND  
IOR#  
IOW#  
UART Channel A  
TXA, RXA, DTRA#,  
32 Byte TX FIFO  
CS#  
UART  
Regs  
DSRA#, RTSA#,  
DTSA#, CDA#, RIA#,  
OP2A#  
IR  
ENDEC  
CHSEL  
TX & RX  
8-bit Data  
Bus  
Interface  
INTA  
INTB  
BRG  
32 Byte RX FIFO  
TXRDYA#  
TXRDYB#  
RXRDYA#  
RXRDYB#  
TXB, RXB, DTRB#,  
DSRB#, RTSB#,  
CTSB#, CDB#, RIB#,  
OP2B#  
UART Channel B  
(same as Channel A)  
Reset  
XTAL1  
XTAL2  
Crystal Osc/Buffer  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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