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XR16L788IQTR PDF预览

XR16L788IQTR

更新时间: 2024-11-07 20:11:07
品牌 Logo 应用领域
艾科嘉 - EXAR 外围集成电路
页数 文件大小 规格书
54页 1068K
描述
Serial I/O Controller, PQFP100

XR16L788IQTR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QFP, QFP100,.7X.9Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-PQFP-G100
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP100,.7X.9
封装形状:RECTANGULAR封装形式:FLATPACK
电源:3.3/5 V认证状态:Not Qualified
子类别:Serial IO/Communication Controllers表面贴装:YES
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.635 mm端子位置:QUAD
uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIALBase Number Matches:1

XR16L788IQTR 数据手册

 浏览型号XR16L788IQTR的Datasheet PDF文件第2页浏览型号XR16L788IQTR的Datasheet PDF文件第3页浏览型号XR16L788IQTR的Datasheet PDF文件第4页浏览型号XR16L788IQTR的Datasheet PDF文件第5页浏览型号XR16L788IQTR的Datasheet PDF文件第6页浏览型号XR16L788IQTR的Datasheet PDF文件第7页 
XR16L788  
HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART  
JULY 2008  
REV. 1.2.3  
FEATURES  
GENERAL DESCRIPTION  
2.97V to 5.5V with 5V Tolerant Inputs Operation  
Single Interrupt Output for all 8 UARTs  
Global Interrupt Source for all 8 UARTs  
5G “Flat” UART Registers for Configurations  
Simultaneous UART Channels Initialization  
The XR16L7881 (788), is a 2.97V to 5.5V with 5V  
tolerant inputs octal Universal Asynchronous  
Receiver and Transmitter (UART). The highly  
integrated device is designed for high bandwidth  
requirement in communication systems. The global  
interrupt source register provides a complete interrupt  
status indication for all 8 channels to speed up  
interrupt parsing. Each UART has its own 16C550  
compatible set of configuration registers, TX and RX  
FIFOs of 64 bytes, fully programmable transmit and  
receive FIFO trigger levels, TX and RX FIFO level  
counters, automatic RTS/CTS or DTR/DSR hardware  
flow control with programmable hysteresis, autoamtic  
software (Xon/Xoff) flow control, RS-485 half-duplex  
direction control with programmable turn-around  
delay, Intel or Motorola bus interface and sleep mode  
with a wake-up indicator.  
Auto RS485 Half-duplex Control with Program-  
mable Turn-around Delay  
A General Purpose 16-bit Timer/Counter  
Sleep Mode with Wake-up Indication  
Highly Integrated Device for Space Saving  
First eight registers are 16C550 compatible  
64-byte Transmit and Receive FIFOs  
Transmit and Receive FIFO Level Counters  
Programmable TX and RX FIFO Trigger Levels  
Automatic RTS/CTS or DTR/DSR Flow Control  
Selectable Hardware Flow Control Hysteresis  
NOTE: Covered by US patents #5,649,122 and #5,949,787  
APPLICATIONS  
Remote Access Servers  
Ethernet Network to Serial Ports  
Network Management  
Factory Automation and Process Control  
Point-of-Sale Systems  
Multi-port RS-232/RS-422/RS-485 Cards  
Automatic Xon/Xoff Software Flow Control with  
Status Indicator  
Infrared (IrDA 1.0) Data Encoder/Decoder  
Programmable Data Rate with Prescaler  
Up to 6.25 Mbps Serial Data Rate at 5V  
100-pin QFP Package (14x20x3 mm)  
FIGURE 1. BLOCK DIAGRAM  
UART Channel 0  
64 Byte TX FIFO  
TX0, RX0, DTR0#,  
UART  
Regs  
IR  
DSR0#, RTS0#,  
CTS0#, CD0#, RI0#  
TX & RX  
ENDEC  
BRG  
64 Byte RX FIFO  
RST#  
A7:A0  
D7:D0  
UART Channel 1  
UART Channel 2  
UART Channel 3  
UART Channel 4  
UART Channel 5  
Data Bus  
Device  
IOR#  
IOW#  
CS#  
Interface  
Configuration  
Registers  
INT#  
16/68#  
UART Channel 6  
TX7, RX7, DTR7#,  
DSR7#, RTS7#,  
UART Channel 7  
16-bit  
Timer/Counter  
CTS7#, CD7#, RI7#  
XTAL1  
XTAL2  
TMRCK  
Crystal Osc/Buffer  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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