XPIO 110GXS
Fully Integrated 10Gbps
Serializer/Deserializer Device
August 2004
Data Sheet
Features
General Description
The XPIO™ 110GXS is a fully integrated 10 Gbps seri-
alizer/deserializer device designed for high-speed
switches and routers that require very low power budget
and a small footprint as well. Centering on 10 Gbps
speed, the XPIO 110GXS is a versatile chip that is
capable of handling applications in various standards,
such as OC-192 (9.95 Gbps) and 10GE (10.31 Gbps).
■ Single chip SERDES solution with
integrated transmitter and receiver
■ Continuous serial operation range from
9.95 Gbps to 10.31 Gbps
■ Parallel LVDS data range from 622 Mbps to
644 Mbps
■ Low power consumption (800 mW typical)
An on-chip low jitter PLL generates all required clocks
based on an external reference clock at 1/16 or 1/64 fre-
quency of the serial data rate, which is 622.08 MHz or
155.52 MHz, respectively, for OC-192 applications. An
Integrated Limiting Amplifier allows flexibility in place-
ment and reduced bit-error rates (BER).
■ Performs 16:1 serialization and 1:16
deserialization
■ Embedded Limiting Amplifier enhances
receiver sensitivity
■ Low-jitter PLL for clock generation
■ On-chip Clock Data Recovery circuit
■ On-chip FIFO to decouple transmit clocks
■ Bit order swap for 10GE operations
Fabricated with state-of-the-art CMOS technology, the
XPIO 110GXS performs all necessary functions for
serial-to-parallel and parallel-to-serial conversions, and
consumes less than one third of the power consumed
by the more conventional SiGe Bi-CMOS designs.
■ Programmable 4-phase LVDS clock output
for easy system design
Overview
■ Repeating serial data output
The XPIO 110GXS consists primarily of blocks of paral-
lel-to-serial and serial-to-parallel functions plus system
timing. Low Voltage Differential Signaling (LVDS) is
used for parallel signal input and output while Current
Mode Logic (CML) is used for serial transmission and
reception. A limiting amplifier is designed into the chip
to improve serial receiver sensitivity. The system timing
blocks consist of the clock-multiplier-unit (CMU), LVPLL
(LVDS interface timing Phase-Lock-Loop) and CDR
(clock-data-recovery) units, which generate clocks for
the chip. Figure 1 shows the XPIO 110GXS chip block
diagram.
■ Line loopback, diagnostic loopback, and
simultaneous loopback modes
■ Frequency Lock Alarm Output
■ Programmable differential output swing on
both Serial driver and Parallel LVDS driver
■ 1.3V core voltage and 2.5V I/O voltage
■ Supports 10GE (10-Gigabit Ethernet),
OC-192, XFP, XSBI and SFI-4.1 interfaces
■ 269-pin flip-chip BGA (15 x 15 mm body
size, 0.8 mm pitch)
■ -40 to85°C operating temperature
Table 1. XPIO 110GXS Supported Protocols
Device
Standards Supported
Data Rate
OC-192
10GE
9.95 Gbps
10.31 Gbps
XPIO 110GXS
© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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