Datasheet > XPIO110GXS

XPIO110GXS

更新时间： 2024-02-18 18:48:17

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
23页	354K
描述
Fully Integrated 10Gbps Serializer/Deserializer Device

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中文翻译

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数据手册

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XPIO110GXS 数据手册

Lattice Semiconductor

XPIO 110GXS Data Sheet

Figure 2. LVDS Loopback Mode Block Diagram

LB_LVDS_ENb=0

BIST_ENb=0

BIST_LB_SC0=0

BIST_LB_SC1=1

RX_D_P

Deserializer

10G RX

RX_D_LV[0..15]

LVDS Data

RX_D_N

RX_CK_LV_P/N

LVDS Data

Loopback

LVDS Clock

Bypass

TX_D_P

Serializer

CMU

10G TX

TX_D_LV[0..15]

TX_CL_LV_P/N

TX_D_N

LVDS Data

REF_CK_P/N

LVDS Line Loopback

Line loopback is a diagnostic mode that establishes a parallel connection between the output of the deserializer

and the input to the serializer. When this mode is active, serial receive data is deserialized, and internally looped

back to the serializer. The data provided at the serializer is transmitted via the CML output. Line loopback is acti-

vated by setting the LB_P622_Enb pin to a logic low.

Mode 1: Synchronous line loopback without clock clean-up. Driving LB_P622_Enb low enables line loopback

mode. Connecting the LVDS output clock, RX_CK_LV_P/N, to REF_CK_P/N makes the loopback mode synchro-

nous. In addition, a separate reference clock is input to RX_REF_CKP/N for use by the CDR logic. The data trans-

mitted across the TX_D_P/N pins is now timed to the LVDS clock making the RX and TX data synchronous.

However, the RX_CK_LV_P/N does not require SONET/SDH tolerance in order to transmit the parallel LVDS data.

This means the data repeated on TX_D_P/N will have signiﬁcant jitter.

Figure 3. Line Loopback Mode 1 Block Diagram

LVDS Loopback

Mode 1

LB_LVDS_ENb=1

BIST_ENb=0

BIST_LB_SC0=0

BIST_LB_SC1=1

RX_D_P

Deserializer

10G RX

RX_D_LV[0..15]

RX_CK_LV_P/N

RX_D_N

LVDS

Data

Parallel

Loopback

LB_P622_ENb=0

TX_D_P

TX_D_N

10G TX

Serializer

TX_D_LV[0..15]

TX_CL_LV_P/N

LVDS

Data

CMU

REF_CK_P/N

1...3 4 567 8 9...23

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