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XPC860DECZP50C1 PDF预览

XPC860DECZP50C1

更新时间: 2024-01-05 23:43:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟外围集成电路
页数 文件大小 规格书
64页 785K
描述
32-BIT, 50MHz, RISC PROCESSOR, PBGA357, PLASTIC, BGA-357

XPC860DECZP50C1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:BGA, BGA357,19X19,50Reach Compliance Code:unknown
风险等级:5.89Is Samacsys:N
JESD-30 代码:S-PBGA-B357JESD-609代码:e0
端子数量:357最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA357,19X19,50封装形状:SQUARE
封装形式:GRID ARRAY电源:3.3 V
认证状态:Not Qualified子类别:Other Microprocessor ICs
标称供电电压:3.3 V表面贴装:YES
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
Base Number Matches:1

XPC860DECZP50C1 数据手册

 浏览型号XPC860DECZP50C1的Datasheet PDF文件第1页浏览型号XPC860DECZP50C1的Datasheet PDF文件第2页浏览型号XPC860DECZP50C1的Datasheet PDF文件第4页浏览型号XPC860DECZP50C1的Datasheet PDF文件第5页浏览型号XPC860DECZP50C1的Datasheet PDF文件第6页浏览型号XPC860DECZP50C1的Datasheet PDF文件第7页 
Ñ Selectable write protection  
Ñ On-chip bus arbitration logic  
General-purpose timers  
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Ñ Four 16-bit timers or two 32-bit timers  
Ñ Gate mode can enable/disable counting  
Ñ Interrupt can be masked on reference match and event capture  
System integration unit (SIU)  
Ñ Bus monitor  
Ñ Software watchdog  
Ñ Periodic interrupt timer (PIT)  
Ñ Low-power stop mode  
Ñ Clock synthesizer  
Ñ PowerPC decrementer, time base, and real-time clock (RTC)  
Ñ Reset controller  
Ñ IEEE 1149.1 test access port (JTAG)  
Interrupts  
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Ñ Seven external interrupt request (IRQ) lines  
Ñ 12 port pins with interrupt capability  
Ñ 23 internal interrupt sources  
Ñ Programmable priority between SCCs  
Ñ Programmable highest priority request  
Communications processor module (CPM)  
Ñ RISC communications processor (CP)  
Ñ Communication-speciÞc commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT  
MODE, and RESTART TRANSMIT)  
Ñ Supports continuous mode transmission and reception on all serial channels  
Ñ Up to 5 Kbytes of dual-port RAM  
Ñ 16 serial DMA (SDMA) channels  
Ñ Three parallel I/O registers with open-drain capability  
On-chip 16x16 multiply accumulate controller (MAC)  
Ñ One operation per clock (two clock latency, one clock blockage)  
Ñ MAC operates concurrently with other instructions  
Ñ FIR loop: four clocks per four multiplies  
Four baud-rate generators (BRGs)  
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Ñ Independent (can be connected to any SCC or SMC)  
Ñ Allow changes during operation  
Ñ Autobaud support option  
Four serial communications controllers (SCCs)  
MOTOROLA  
MPC860 Hardware SpeciÞcations  
3

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