5秒后页面跳转
捷配首页

Datasheet > XCV2000E-8FG860I
XCV2000E-8FG860I PDF预览

XCV2000E-8FG860I

更新时间： 2024-11-04 22:49:15
品牌 Logo 应用领域
赛灵思 - XILINX 现场可编程门阵列栅
页数 文件大小 规格书
5页 89K
描述
Virtex-E 1.8 V Field Programmable Gate Arrays

阅读下载

中文翻译

获取价格

XCV2000E-8FG860I 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：FBGA-860
针数：860Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.85
最大时钟频率：416 MHzCLB-Max的组合延迟：0.4 ns
JESD-30 代码：S-PBGA-B860JESD-609代码：e0
长度：42.5 mm湿度敏感等级：3
可配置逻辑块数量：9600等效关口数量：518400
输入次数：660逻辑单元数量：43200
输出次数：660端子数量：860
组织：9600 CLBS, 518400 GATES封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA860,42X42,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：225电源：1.2/3.6,1.8 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
座面最大高度：2.2 mm子类别：Field Programmable Gate Arrays
最大供电电压：1.89 V最小供电电压：1.71 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS端子面层：Tin/Lead (Sn63Pb37)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：42.5 mmBase Number Matches：1

XCV2000E-8FG860I 数据手册

 浏览型号XCV2000E-8FG860I的Datasheet PDF文件第2页浏览型号XCV2000E-8FG860I的Datasheet PDF文件第3页浏览型号XCV2000E-8FG860I的Datasheet PDF文件第4页浏览型号XCV2000E-8FG860I的Datasheet PDF文件第5页 
0
R
Virtex™-E 1.8 V  
Field Programmable Gate Arrays  
0
0
DS022-1 (v2.2) November 9, 2001  
Preliminary Product Specification  
Features  
•
Fast, High-Density 1.8 V FPGA Family  
•
High-Performance Built-In Clock Management Circuitry  
-
-
-
-
Densities from 58 k to 4 M system gates  
-
-
Eight fully digital Delay-Locked Loops (DLLs)  
130 MHz internal performance (four LUT levels)  
Designed for low-power operation  
Digitally-Synthesized 50% duty cycle for Double  
Data Rate (DDR) Applications  
-
-
Clock Multiply and Divide  
PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz  
Zero-delay conversion of high-speed LVPECL/LVDS  
clocks to any I/O standard  
•
•
Highly Flexible SelectI/O+™ Technology  
-
-
Supports 20 high-performance interface standards  
•
Flexible Architecture Balances Speed and Density  
Up to 804 singled-ended I/Os or 344 differential I/O  
pairs for an aggregate bandwidth of > 100 Gb/s  
-
-
-
-
Dedicated carry logic for high-speed arithmetic  
Dedicated multiplier support  
Differential Signalling Support  
Cascade chain for wide-input function  
-
-
-
-
LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL  
Differential I/O signals can be input, output, or I/O  
Compatible with standard differential devices  
Abundant registers/latches with clock enable, and  
dual synchronous/asynchronous set and reset  
-
-
-
Internal 3-state bussing  
LVPECL and LVDS clock inputs for 300+ MHz  
clocks  
IEEE 1149.1 boundary-scan logic  
Die-temperature sensor diode  
•
•
Proprietary High-Performance SelectLink™  
Technology  
•
Supported by Xilinx Foundation™ and Alliance Series™  
Development Systems  
-
-
Double Data Rate (DDR) to Virtex-E link  
Web-based HDL generation methodology  
-
-
Further compile time reduction of 50%  
Internet Team Design (ITD) tool ideal for  
million-plus gate density designs  
Sophisticated SelectRAM+™ Memory Hierarchy  
-
-
-
-
1 Mb of internal configurable distributed RAM  
Up to 832 Kb of synchronous internal block RAM  
True Dual-Port™ BlockRAM capability  
-
Wide selection of PC and workstation platforms  
•
•
SRAM-Based In-System Configuration  
Unlimited re-programmability  
Advanced Packaging Options  
-
Memory bandwidth up to 1.66 Tb/s (equivalent  
bandwidth of over 100 RAMBUS channels)  
-
-
-
-
0.8 mm Chip-scale  
1.0 mm BGA  
1.27 mm BGA  
HQ/PQ  
-
Designed for high-performance Interfaces to  
External Memories  
-
-
-
200 MHz ZBT* SRAMs  
200 Mb/s DDR SDRAMs  
Supported by free Synthesizable reference design  
•
•
0.18 m 6-Layer Metal Process  
100% Factory Tested  
* ZBT is a trademark of Integrated Device Technology, Inc.  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS022-1 (v2.2) November 9, 2001  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
1
12345

中文翻译

下载PDF

与XCV2000E-8FG860I相关器件

型号 品牌 获取价格 描述 数据表
XCV2000E-8FGG1156I XILINX

获取价格

 		Field Programmable Gate Array, 9600 CLBs, 518400 Gates, 416MHz, 43200-Cell, CMOS, PBGA1156
XCV2000E-8HQ240C XILINX

获取价格

 		Virtex-E 1.8 V Field Programmable Gate Arrays
XCV2000E-8HQ240I XILINX

获取价格

 		Virtex-E 1.8 V Field Programmable Gate Arrays
XCV200-4BG256C XILINX

获取价格

 		Field Programmable Gate Arrays
XCV200-4BG256I XILINX

获取价格

 		Field Programmable Gate Arrays
XCV200-4BG352C XILINX

获取价格

 		Field Programmable Gate Arrays
XCV200-4BG352I XILINX

获取价格

 		Field Programmable Gate Arrays
XCV200-4BGG256C XILINX

获取价格

 		Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 250MHz, CMOS, PBGA256, BGA-256
XCV200-4FG256C XILINX

获取价格

 		Field Programmable Gate Arrays
XCV200-4FG256I XILINX

获取价格

 		Field Programmable Gate Arrays

与XCV2000E-8FG860I相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证