Datasheet > XCV200-4HQ240C

XCV200-4HQ240C

更新时间： 2024-11-07 05:59:43

品牌	Logo	应用领域
赛灵思 - XILINX		栅
页数	文件大小	规格书
71页	452K
描述
Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 250MHz, PQFP240, HQ240

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XCV200-4HQ240C 数据手册

Virtex™ 2.5 V

Field Programmable Gate Arrays

DS003-2 (v2.5) April 2, 2001

Product Specification

The output buffer and all of the IOB control signals have

independent polarity controls.

Architectural Description

Virtex Array

The Virtex user-programmable gate array, shown in

Figure 1, comprises two major configurable elements: con-

figurable logic blocks (CLBs) and input/output blocks

(IOBs).

DLL

IOBs

DLL

VersaRing

•

CLBs provide the functional elements for constructing

logic

•

IOBs provide the interface between the package pins

and the CLBs

CLBs

CLBs interconnect through a general routing matrix (GRM).

The GRM comprises an array of routing switches located at

the intersections of horizontal and vertical routing channels.

Each CLB nests into a VersaBlock™ that also provides local

routing resources to connect the CLB to the GRM.

The VersaRing™ I/O interface provides additional routing

resources around the periphery of the device. This routing

improves I/O routability and facilitates pin locking.

VersaRing

IOBs

DLL

The Virtex architecture also includes the following circuits

that connect to the GRM.

vao_b.eps

•

Dedicated block memories of 4096 bits each

Figure 1: Virtex Architecture Overview

Clock DLLs for clock-distribution delay compensation

and clock domain control

All pads are protected against damage from electrostatic

discharge (ESD) and from over-voltage transients. Two

forms of over-voltage protection are provided, one that per-

mits 5 V compliance, and one that does not. For 5 V compli-

ance, a Zener-like structure connected to ground turns on

when the output rises to approximately 6.5 V. When PCI

3.3 V compliance is required, a conventional clamp diode is

•

3-State buffers (BUFTs) associated with each CLB that

drive dedicated segmentable horizontal routing

resources

Values stored in static memory cells control the configurable

logic elements and interconnect resources. These values

load into the memory cells on power-up, and can reload if

necessary to change the function of the device.

connected to the output supply voltage, V_CCO

Input/Output Block

Optional pull-up and pull-down resistors and an optional

weak-keeper circuit are attached to each pad. Prior to con-

figuration, all pins not involved in configuration are forced

into their high-impedance state. The pull-down resistors and

the weak-keeper circuits are inactive, but inputs can option-

ally be pulled up.

The Virtex IOB, Figure 2, features SelectIO™ inputs and

outputs that support a wide variety of I/O signalling stan-

dards, see Table 1.

The three IOB storage elements function either as edge-trig-

gered D-type flip-flops or as level sensitive latches. Each

IOB has a clock signal (CLK) shared by the three flip-flops

and independent clock enable signals for each flip-flop.

The activation of pull-up resistors prior to configuration is

controlled on a global basis by the configuration mode pins.

If the pull-up resistors are not activated, all the pins will float.

Consequently, external pull-up or pull-down resistors must

be provided on pins required to be at a well-defined logic

level prior to configuration.

In addition to the CLK and CE control signals, the three

flip-flops share a Set/Reset (SR). For each flip-flop, this sig-

nal can be independently configured as a synchronous Set,

a synchronous Reset, an asynchronous Preset, or an asyn-

chronous Clear.

All Virtex IOBs support IEEE 1149.1-compatible boundary

scan testing.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS003-2 (v2.5) April 2, 2001

Product Specification

www.xilinx.com

1-800-255-7778

Module 2 of 4

12 3 4 5 6 7...71

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与XCV200-4HQ240C相关器件

型号	品牌	获取价格	描述	数据表
XCV200-4PQ240C	XILINX	获取价格	Field Programmable Gate Arrays
XCV200-4PQ240I	XILINX	获取价格	Field Programmable Gate Arrays
XCV200-4PQG240C	XILINX	获取价格	Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 250MHz, CMOS, PQFP240, PLASTIC, QF
XCV200-4PQG240I	XILINX	获取价格	Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 250MHz, CMOS, PQFP240, PLASTIC, QF
XCV200-5BG256C	XILINX	获取价格	Field Programmable Gate Arrays
XCV200-5BG256I	XILINX	获取价格	Field Programmable Gate Arrays
XCV200-5BG352C	XILINX	获取价格	Field Programmable Gate Arrays
XCV200-5BG352I	XILINX	获取价格	Field Programmable Gate Arrays
XCV200-5BGG256C	XILINX	获取价格	Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 294MHz, CMOS, PBGA256, BGA-256
XCV200-5BGG352C	XILINX	获取价格	Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 294MHz, CMOS, PBGA352, BGA-352

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