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XCV200-4PQ240C

更新时间： 2024-11-05 22:34:55
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赛灵思 - XILINX 现场可编程门阵列可编程逻辑栅时钟
页数 文件大小 规格书
4页 40K
描述
Field Programmable Gate Arrays

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XCV200-4PQ240C 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：PLASTIC, QFP-240针数：240
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.79
Is Samacsys：N最大时钟频率：250 MHz
CLB-Max的组合延迟：0.8 nsJESD-30 代码：S-PQFP-G240
JESD-609代码：e0长度：32 mm
湿度敏感等级：3可配置逻辑块数量：1176
等效关口数量：236666输入次数：166
逻辑单元数量：5292输出次数：166
端子数量：240最高工作温度：85 °C
最低工作温度：组织：1176 CLBS, 236666 GATES
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装等效代码：QFP240,1.3SQ,20封装形状：SQUARE
封装形式：FLATPACK, FINE PITCH峰值回流温度（摄氏度）：225
电源：1.2/3.6,2.5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：4.1 mm
子类别：Field Programmable Gate Arrays最大供电电压：2.625 V
最小供电电压：2.375 V标称供电电压：2.5 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：32 mmBase Number Matches：1

XCV200-4PQ240C 数据手册

 浏览型号XCV200-4PQ240C的Datasheet PDF文件第2页浏览型号XCV200-4PQ240C的Datasheet PDF文件第3页浏览型号XCV200-4PQ240C的Datasheet PDF文件第4页 
0
R
Virtex™ 2.5 V  
Field Programmable Gate Arrays  
0
3
DS003-1 (v2.5 ) April 2, 2001  
Product Specification  
Features  
•
Fast, high-density Field-Programmable Gate Arrays  
•
•
Supported by FPGA Foundation™ and Alliance  
Development Systems  
-
-
-
-
Densities from 50k to 1M system gates  
System performance up to 200 MHz  
66-MHz PCI Compliant  
-
Complete support for Unified Libraries, Relationally  
Placed Macros, and Design Manager  
-
Wide selection of PC and workstation platforms  
Hot-swappable for Compact PCI  
SRAM-based in-system configuration  
•
•
Multi-standard SelectIO™ interfaces  
-
-
Unlimited re-programmability  
Four programming modes  
-
-
16 high-performance interface standards  
Connects directly to ZBTRAM devices  
•
•
0.22 m 5-layer metal process  
100% factory tested  
Built-in clock-management circuitry  
-
Four dedicated delay-locked loops (DLLs) for  
advanced clock control  
Description  
-
Four primary low-skew global clock distribution  
nets, plus 24 secondary local clock nets  
The Virtex FPGA family delivers high-performance,  
high-capacity programmable logic solutions. Dramatic  
increases in silicon efficiency result from optimizing the new  
architecture for place-and-route efficiency and exploiting an  
aggressive 5-layer-metal 0.22 m CMOS process. These  
advances make Virtex FPGAs powerful and flexible alterna-  
tives to mask-programmed gate arrays. The Virtex family  
comprises the nine members shown in Table 1.  
•
•
Hierarchical memory system  
-
-
-
LUTs configurable as 16-bit RAM, 32-bit RAM,  
16-bit dual-ported RAM, or 16-bit Shift Register  
Configurable synchronous dual-ported 4k-bit  
RAMs  
Fast interfaces to external high-performance RAMs  
Flexible architecture that balances speed and density  
-
-
-
-
Dedicated carry logic for high-speed arithmetic  
Dedicated multiplier support  
Cascade chain for wide-input functions  
Abundant registers/latches with clock enable, and  
dual synchronous/asynchronous set and reset  
Internal 3-state bussing  
Building on experience gained from previous generations of  
FPGAs, the Virtex family represents a revolutionary step  
forward in programmable logic design. Combining a wide  
variety of programmable system features, a rich hierarchy of  
fast, flexible interconnect resources, and advanced process  
technology, the Virtex family delivers a high-speed and  
high-capacity programmable logic solution that enhances  
design flexibility while reducing time-to-market.  
-
-
-
IEEE 1149.1 boundary-scan logic  
Die-temperature sensor diode  
Table 1: Virtex Field-Programmable Gate Array Family Members  
Maximum  
Block RAM  
Bits  
Maximum  
SelectRAM+™ Bits  
Device  
System Gates  
CLB Array  
Logic Cells  
Available I/O  
XCV50  
57,906  
16x24  
1,728  
180  
180  
260  
284  
316  
404  
512  
512  
512  
32,768  
40,960  
49,152  
57,344  
65,536  
81,920  
98,304  
114,688  
131,072  
24,576  
38,400  
55,296  
75,264  
98,304  
153,600  
221,184  
301,056  
393,216  
XCV100  
XCV150  
XCV200  
XCV300  
XCV400  
XCV600  
XCV800  
XCV1000  
108,904  
20x30  
2,700  
164,674  
24x36  
3,888  
236,666  
28x42  
5,292  
322,970  
32x48  
6,912  
468,252  
40x60  
10,800  
15,552  
21,168  
27,648  
661,111  
48x72  
888,439  
56x84  
1,124,022  
64x96  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS003-1 (v2.5 ) April 2, 2001  
Product Specification  
www.xilinx.com  
1-800-255-7778  
Module 1 of 4  
1
1234

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XCV200-4PQ240C 替代型号

型号 品牌 替代类型 描述 数据表
XCV200-5PQ240I XILINX

完全替代

 Field Programmable Gate Arrays
XCV200-5PQ240C XILINX

完全替代

 Field Programmable Gate Arrays
XCV200-4PQ240I XILINX

完全替代

 Field Programmable Gate Arrays

与XCV200-4PQ240C相关器件

型号 品牌 获取价格 描述 数据表
XCV200-4PQ240I XILINX

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 		Field Programmable Gate Arrays
XCV200-4PQG240C XILINX

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 		Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 250MHz, CMOS, PQFP240, PLASTIC, QF
XCV200-4PQG240I XILINX

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 		Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 250MHz, CMOS, PQFP240, PLASTIC, QF
XCV200-5BG256C XILINX

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 		Field Programmable Gate Arrays
XCV200-5BG256I XILINX

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 		Field Programmable Gate Arrays
XCV200-5BG352C XILINX

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 		Field Programmable Gate Arrays
XCV200-5BG352I XILINX

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 		Field Programmable Gate Arrays
XCV200-5BGG256C XILINX

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 		Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 294MHz, CMOS, PBGA256, BGA-256
XCV200-5BGG352C XILINX

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 		Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 294MHz, CMOS, PBGA352, BGA-352
XCV200-5FG256C XILINX

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 		Field Programmable Gate Arrays

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