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XCV200-5FGG256I PDF预览

XCV200-5FGG256I

更新时间: 2024-11-06 19:48:43
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
99页 927K
描述
Field Programmable Gate Array, 1176 CLBs, 236666 Gates, 294MHz, CMOS, PBGA256, FBGA-256

XCV200-5FGG256I 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:256
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
最大时钟频率:294 MHzCLB-Max的组合延迟:0.7 ns
JESD-30 代码:S-PBGA-B256JESD-609代码:e1
长度:17 mm湿度敏感等级:3
可配置逻辑块数量:1176等效关口数量:236666
端子数量:256组织:1176 CLBS, 236666 GATES
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):260可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:2 mm
最大供电电压:2.625 V最小供电电压:2.375 V
标称供电电压:2.5 V表面贴装:YES
技术:CMOS端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:17 mmBase Number Matches:1

XCV200-5FGG256I 数据手册

 浏览型号XCV200-5FGG256I的Datasheet PDF文件第2页浏览型号XCV200-5FGG256I的Datasheet PDF文件第3页浏览型号XCV200-5FGG256I的Datasheet PDF文件第4页浏览型号XCV200-5FGG256I的Datasheet PDF文件第5页浏览型号XCV200-5FGG256I的Datasheet PDF文件第6页浏览型号XCV200-5FGG256I的Datasheet PDF文件第7页 
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Spartan-II FPGA Family  
Data Sheet  
DS001 June 13, 2008  
Product Specification  
This document includes all four modules of the Spartan®-II FPGA data sheet.  
Module 1:  
Introduction and Ordering Information  
Module 3:  
DC and Switching Characteristics  
DS001-1 (v2.8) June 13, 2008  
DS001-3 (v2.8) June 13, 2008  
Introduction  
DC Specifications  
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Absolute Maximum Ratings  
Recommended Operating Conditions  
DC Characteristics  
Power-On Requirements  
DC Input and Output Levels  
Features  
General Overview  
Product Availability  
User I/O Chart  
Ordering Information  
Switching Characteristics  
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Pin-to-Pin Parameters  
Module 2:  
IOB Switching Characteristics  
Clock Distribution Characteristics  
DLL Timing Parameters  
CLB Switching Characteristics  
Block RAM Switching Characteristics  
TBUF Switching Characteristics  
JTAG Switching Characteristics  
Functional Description  
DS001-2 (v2.8) June 13, 2008  
Architectural Description  
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-
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Spartan-II Array  
Input/Output Block  
Configurable Logic Block  
Block RAM  
Clock Distribution: Delay-Locked Loop  
Boundary Scan  
Module 4:  
Pinout Tables  
Development System  
Configuration  
DS001-4 (v2.8) June 13, 2008  
Pin Definitions  
Pinout Tables  
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Configuration Timing  
Design Considerations  
IMPORTANT NOTE: This Spartan-II FPGA data sheet is in four modules. Each module has its own Revision History at the  
end. Use the PDF "Bookmarks" for easy navigation in this volume.  
© 2000-2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other  
trademarks are the property of their respective owners.  
DS001 June 13, 2008  
www.xilinx.com  
Product Specification  
1

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