Datasheet > XCV2000E-7HQ240C

XCV2000E-7HQ240C

更新时间： 2024-11-04 22:22:51

品牌	Logo	应用领域
赛灵思 - XILINX		现场可编程门阵列栅
页数	文件大小	规格书
5页	89K
描述
Virtex-E 1.8 V Field Programmable Gate Arrays

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XCV2000E-7HQ240C 数据手册

Virtex™-E 1.8 V

Field Programmable Gate Arrays

DS022-1 (v2.2) November 9, 2001

Preliminary Product Specification

Features

•

Fast, High-Density 1.8 V FPGA Family

•

High-Performance Built-In Clock Management Circuitry

Densities from 58 k to 4 M system gates

Eight fully digital Delay-Locked Loops (DLLs)

130 MHz internal performance (four LUT levels)

Designed for low-power operation

Digitally-Synthesized 50% duty cycle for Double

Data Rate (DDR) Applications

Clock Multiply and Divide

PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz

Zero-delay conversion of high-speed LVPECL/LVDS

clocks to any I/O standard

•

Highly Flexible SelectI/O+™ Technology

Supports 20 high-performance interface standards

•

Flexible Architecture Balances Speed and Density

Up to 804 singled-ended I/Os or 344 differential I/O

pairs for an aggregate bandwidth of > 100 Gb/s

Dedicated carry logic for high-speed arithmetic

Dedicated multiplier support

Differential Signalling Support

Cascade chain for wide-input function

LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL

Differential I/O signals can be input, output, or I/O

Compatible with standard differential devices

Abundant registers/latches with clock enable, and

dual synchronous/asynchronous set and reset

Internal 3-state bussing

LVPECL and LVDS clock inputs for 300+ MHz

clocks

IEEE 1149.1 boundary-scan logic

Die-temperature sensor diode

•

Proprietary High-Performance SelectLink™

Technology

•

Supported by Xilinx Foundation™ and Alliance Series™

Development Systems

Double Data Rate (DDR) to Virtex-E link

Web-based HDL generation methodology

Further compile time reduction of 50%

Internet Team Design (ITD) tool ideal for

million-plus gate density designs

Sophisticated SelectRAM+™ Memory Hierarchy

1 Mb of internal configurable distributed RAM

Up to 832 Kb of synchronous internal block RAM

True Dual-Port™ BlockRAM capability

Wide selection of PC and workstation platforms

•

SRAM-Based In-System Configuration

Unlimited re-programmability

Advanced Packaging Options

Memory bandwidth up to 1.66 Tb/s (equivalent

bandwidth of over 100 RAMBUS channels)

0.8 mm Chip-scale

1.0 mm BGA

1.27 mm BGA

HQ/PQ

Designed for high-performance Interfaces to

External Memories

200 MHz ZBT* SRAMs

200 Mb/s DDR SDRAMs

Supported by free Synthesizable reference design

•

0.18 m 6-Layer Metal Process

100% Factory Tested

* ZBT is a trademark of Integrated Device Technology, Inc.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS022-1 (v2.2) November 9, 2001

Preliminary Product Specification

www.xilinx.com

1-800-255-7778

Module 1 of 4

12 3 4 5

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与XCV2000E-7HQ240C相关器件

型号	品牌	获取价格	描述	数据表
XCV2000E-7HQ240I	XILINX	获取价格	Virtex-E 1.8 V Field Programmable Gate Arrays
XCV2000E-8BG240C	XILINX	获取价格	Virtex-E 1.8 V Field Programmable Gate Arrays
XCV2000E-8BG240I	XILINX	获取价格	Virtex-E 1.8 V Field Programmable Gate Arrays
XCV2000E-8BG560C	XILINX	获取价格	Virtex-E 1.8 V Field Programmable Gate Arrays
XCV2000E-8BG560I	XILINX	获取价格	Virtex-E 1.8 V Field Programmable Gate Arrays
XCV2000E-8FG1156C	XILINX	获取价格	Virtex-E 1.8 V Field Programmable Gate Arrays
XCV2000E-8FG1156I	XILINX	获取价格	Virtex-E 1.8 V Field Programmable Gate Arrays
XCV2000E-8FG240C	XILINX	获取价格	Virtex-E 1.8 V Field Programmable Gate Arrays
XCV2000E-8FG240I	XILINX	获取价格	Virtex-E 1.8 V Field Programmable Gate Arrays
XCV2000E-8FG680C	XILINX	获取价格	Virtex-E 1.8 V Field Programmable Gate Arrays

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