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XC3S200A-4FTG256C PDF预览

XC3S200A-4FTG256C

更新时间: 2024-09-19 15:58:15
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
132页 3936K
描述
Field Programmable Gate Array, 448 CLBs, 200000 Gates, 250MHz, 4032-Cell, CMOS, PBGA256, LEAD FREE, FPTBGA-256

XC3S200A-4FTG256C 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:LBGA, BGA256,16X16,40针数:256
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:12 weeks
风险等级:0.69最大时钟频率:667 MHz
CLB-Max的组合延迟:0.71 nsJESD-30 代码:S-PBGA-B256
JESD-609代码:e1长度:17 mm
湿度敏感等级:3可配置逻辑块数量:448
等效关口数量:200000输入次数:195
逻辑单元数量:4032输出次数:160
端子数量:256最高工作温度:85 °C
最低工作温度:组织:448 CLBS, 200000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装等效代码:BGA256,16X16,40封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE峰值回流温度(摄氏度):260
电源:1.2,2.5/3.3 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:1.55 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.26 V
最小供电电压:1.14 V标称供电电压:1.2 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:17 mmBase Number Matches:1

XC3S200A-4FTG256C 数据手册

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Spartan-3A FPGA Family:  
Data Sheet  
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DS529 August 19, 2010  
Product Specification  
Module 1:  
Introduction and Ordering Information  
Module 3:  
DC and Switching Characteristics  
DS529-1 (v2.0) August 19, 2010  
DS529-3 (v2.0) August 19, 2010  
Introduction  
Features  
DC Electrical Characteristics  
Absolute Maximum Ratings  
Supply Voltage Specifications  
Recommended Operating Conditions  
Architectural and Configuration Overview  
General I/O Capabilities  
Production Status  
Supported Packages and Package Marking  
Ordering Information  
Switching Characteristics  
I/O Timing  
Configurable Logic Block (CLB) Timing  
Multiplier Timing  
Block RAM Timing  
Module 2:  
Digital Clock Manager (DCM) Timing  
Suspend Mode Timing  
Device DNA Timing  
Spartan-3A FPGA Family: Functional  
Description  
Configuration and JTAG Timing  
DS529-2 (v2.0) August 19, 2010  
The functionality of the Spartan®-3A FPGA family is  
described in the following documents.  
Module 4:  
Pinout Descriptions  
UG331: Spartan-3 Generation FPGA User Guide  
DS529-4 (v2.0) August 19, 2010  
Clocking Resources  
Digital Clock Managers (DCMs)  
Block RAM  
Pin Descriptions  
Package Overview  
Pinout Tables  
Configurable Logic Blocks (CLBs)  
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-
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Distributed RAM  
SRL16 Shift Registers  
Carry and Arithmetic Logic  
Footprint Diagrams  
For more information on the Spartan-3A FPGA family, go to  
www.xilinx.com/spartan3a  
I/O Resources  
Embedded Multiplier Blocks  
Programmable Interconnect  
ISE® Design Tools and IP Cores  
Embedded Processing and Control Solutions  
Pin Types and Package Overview  
Package Drawings  
Spartan-3A FPGA  
XC3S50A  
Status  
Production  
Production  
Production  
Production  
Production  
Powering FPGAs  
Power Management  
XC3S200A  
UG332: Spartan-3 Generation Configuration User Guide  
XC3S400A  
Configuration Overview  
Configuration Pins and Behavior  
Bitstream Sizes  
XC3S700A  
XC3S1400A  
Detailed Descriptions by Mode  
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-
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Master Serial Mode using Platform Flash PROM  
Master SPI Mode using Commodity Serial Flash  
Master BPI Mode using Commodity Parallel Flash  
Slave Parallel (SelectMAP) using a Processor  
Slave Serial using a Processor  
JTAG Mode  
ISE iMPACT Programming Examples  
MultiBoot Reconfiguration  
Design Authentication using Device DNA  
UG334: Spartan-3A/3AN FPGA Starter Kit User Guide  
© Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and  
other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners.  
DS529 August 19, 2010  
www.xilinx.com  
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Product Specification  

XC3S200A-4FTG256C 替代型号

型号 品牌 替代类型 描述 数据表
XC3S200A-4FTG256I XILINX

完全替代

Field Programmable Gate Array, 448 CLBs, 200000 Gates, 250MHz, 4032-Cell, CMOS, PBGA256, L

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