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XC1802VQ44I

更新时间： 2024-11-11 19:25:59
品牌 Logo 应用领域
赛灵思 - XILINX 时钟内存集成电路
页数 文件大小 规格书
16页 114K
描述
Configuration Memory, 2MX1, 45ns, Parallel, CMOS, PQFP44, PLASTIC, VQFP-44

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中文翻译

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XC1802VQ44I 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, VQFP-44
针数：44Reach Compliance Code：not_compliant
ECCN代码：3A991.B.1.AHTS代码：8542.39.00.01
风险等级：5.89最长访问时间：45 ns
其他特性：SERIAL MODE ALSO AVAILABLE最大时钟频率 (fCLK)：15 MHz
数据保留时间-最小值：10耐久性：10000 Write/Erase Cycles
JESD-30 代码：S-PQFP-G44JESD-609代码：e0
长度：10 mm内存密度：2097152 bit
内存集成电路类型：CONFIGURATION MEMORY内存宽度：1
湿度敏感等级：3功能数量：1
端子数量：44字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：2MX1封装主体材料：PLASTIC/EPOXY
封装代码：TQFP封装等效代码：TQFP44,.47SQ,32
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE
并行/串行：PARALLEL电源：2.5/3.3,3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.0001 A子类别：Flash Memories
最大压摆率：0.03 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD类型：NOR TYPE
宽度：10 mmBase Number Matches：1

XC1802VQ44I 数据手册

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d
0
XC1800 Series of In-System  
Programmable Configuration  
PROMs  
0
6*  
September 17, 1999 (Version 1.3)  
Preliminary Product Specification  
Features  
Description  
•
In-system programmable 3.3V PROMs for configuration  
of Xilinx FPGAs  
Xilinx introduces the XC1800 series of in-system program-  
mable configuration PROMs. Initial devices in this 3.3V  
family are a 4 megabit, a 2 megabit, a 1 megabit, a 512  
Kbit, a 256 Kbit, and a 128 Kbit PROM that provide an  
easy-to-use, cost-effective method for re-programming and  
storing large Xilinx FPGA or CPLD configuration bit-  
streams.  
-
-
Endurance of 10,000 program/erase cycles  
Program/erase over full commercial voltage and  
temperature range  
•
•
IEEE Std 1149.1 boundary-scan (JTAG) support  
Simple interface to the FPGA; could be configured to  
use only one user I/O pin  
Cascadable for storing longer or multiple bitstreams  
Dual configuration modes  
When the FPGA is in Master Serial mode, it generates a  
configuration clock that drives the PROM. A short access  
time after the rising CCLK, data is available on the PROM  
DATA (D0) pin that is connected to the FPGA DIN pin. The  
FPGA generates the appropriate number of clock pulses to  
complete the configuration. When the FPGA is in Slave  
Serial mode, the PROM and the FPGA are clocked by an  
external clock.  
•
•
-
-
Serial Slow/Fast configuration (up to 15 mHz).  
Parallel  
•
•
•
•
•
Low-power advanced CMOS FLASH process  
5 V tolerant I/O pins accept 5 V, 3.3 V and 2.5 V signals.  
3.3 V or 2.5 V output capability  
Available in PC20, SO20, PC44 and VQ44 packages.  
Design support using the Xilinx Alliance and  
Foundation series software packages.  
JTAG command initiation of standard FPGA  
configuration.  
When the FPGA is in Express or SelectMAP Mode, an  
external oscillator will generate the configuration clock that  
drives the PROM and the FPGA. After the rising CCLK  
edge, data are available on the PROM’s DATA (D0-D7)  
pins. The data will be clocked into the FPGA on the follow-  
ing rising edge of the CCLK. Neither Express nor Select-  
MAP utilize a Length Count, so a free-running oscillator  
may be used. See Figure 5  
•
Multiple devices can be concatenated by using the CEO  
output to drive the CE input of the following device. The  
clock inputs and the DATA outputs of all PROMs in this  
chain are interconnected. All devices are compatible and  
can be cascaded with other members of the family or with  
the XC1700L one-time programmable Serial PROM family.  
OE/Reset  
CLK CE  
TCK  
Data  
Control  
and  
JTAG  
CEO  
Serial  
or  
Parallel  
Interface  
TMS  
TDI  
Memory  
D0 DATA  
(Serial or Parallel  
(Express/SelectMAP) Mode)  
Data  
Address  
Interface  
TDO  
D1 - D7  
Express Mode and  
SelectMAP Interface  
CF  
99020300  
Figure 1: XC1800 Series Block Diagram  
September 17, 1999 (Version 1.3)  
1
1234567...16

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 		In-System Programmable Configuration PROMs

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