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XA3S200-4PQG208I PDF预览

XA3S200-4PQG208I

更新时间: 2024-09-19 21:16:19
品牌 Logo 应用领域
赛灵思 - XILINX 时钟可编程逻辑
页数 文件大小 规格书
272页 5986K
描述
Field Programmable Gate Array, 480 CLBs, 200000 Gates, 125MHz, 4320-Cell, PQFP208, LEAD FREE, PLASTIC, QFP-208

XA3S200-4PQG208I 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:FQFP, QFP208,1.2SQ,20针数:208
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.78
最大时钟频率:125 MHzJESD-30 代码:S-PQFP-G208
JESD-609代码:e3长度:28 mm
湿度敏感等级:3可配置逻辑块数量:480
等效关口数量:200000输入次数:173
逻辑单元数量:4320输出次数:173
端子数量:208最高工作温度:100 °C
最低工作温度:-40 °C组织:480 CLBS, 200000 GATES
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH峰值回流温度(摄氏度):245
电源:1.2,1.2/3.3,2.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified筛选级别:AEC-Q100
座面最大高度:4.1 mm子类别:Field Programmable Gate Arrays
最大供电电压:1.26 V最小供电电压:1.14 V
标称供电电压:1.2 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:28 mmBase Number Matches:1

XA3S200-4PQG208I 数据手册

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1
Spartan-3 FPGA Family  
Data Sheet  
DS099 June 27, 2013  
Product Specification  
Module 1:  
Introduction and Ordering Information  
Module 4: Pinout Descriptions  
DS099 (v3.1) June 27, 2013  
DS099 (v3.1) June 27, 2013  
Pin Descriptions  
Pin Behavior During Configuration  
Introduction  
Features  
Package Overview  
Pinout Tables  
Architectural Overview  
Array Sizes and Resources  
User I/O Chart  
Footprints  
Ordering Information  
Module 2: Functional Description  
DS099 (v3.1) June 27, 2013  
Input/Output Blocks (IOBs)  
IOB Overview  
SelectIO™ Interface I/O Standards  
Configurable Logic Blocks (CLBs)  
Block RAM  
Dedicated Multipliers  
Digital Clock Manager (DCM)  
Clock Network  
Configuration  
Module 3:  
DC and Switching Characteristics  
DS099 (v3.1) June 27, 2013  
DC Electrical Characteristics  
Absolute Maximum Ratings  
Supply Voltage Specifications  
Recommended Operating Conditions  
DC Characteristics  
Switching Characteristics  
I/O Timing  
Internal Logic Timing  
DCM Timing  
Configuration and JTAG Timing  
© Copyright 2003–2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx  
in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.  
DS099 June 27, 2013  
www.xilinx.com  
Product Specification  
1

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