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X5325S8IZ-4.5A-T1 PDF预览

X5325S8IZ-4.5A-T1

更新时间： 2024-11-26 14:36:51
品牌 Logo 应用领域
瑞萨 - RENESAS 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
21页 359K
描述
IC,SERIAL EEPROM,4KX8,CMOS,SOP,8PIN,PLASTIC

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X5325S8IZ-4.5A-T1 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Transferred包装说明：SOP, SOP8,.25
Reach Compliance Code：compliant风险等级：5.63
Is Samacsys：N数据保留时间-最小值：100
耐久性：100000 Write/Erase CyclesJESD-30 代码：R-PDSO-G8
JESD-609代码：e3内存密度：32768 bit
内存集成电路类型：EEPROM内存宽度：8
湿度敏感等级：1端子数量：8
字数：4096 words字数代码：4000
最高工作温度：85 °C最低工作温度：-40 °C
组织：4KX8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：SERIAL峰值回流温度（摄氏度）：225
电源：5 V认证状态：Not Qualified
串行总线类型：SPI最大待机电流：0.000001 A
子类别：EEPROMs最大压摆率：0.005 mA
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED写保护：HARDWARE/SOFTWARE
Base Number Matches：1

X5325S8IZ-4.5A-T1 数据手册

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X5323, X5325  
®
(Replaces X25323, X25325)  
Data Sheet  
October 27, 2005  
FN8131.1  
DESCRIPTION  
CPU Supervisor with 32Kb SPI EEPROM  
These devices combine four popular functions, Power-on  
Reset Control, Watchdog Timer, Supply Voltage  
Supervision, and Block Lock Protect Serial EEPROM  
Memory in one package. This combination lowers  
system cost, reduces board space requirements, and  
increases reliability.  
FEATURES  
• Selectable watchdog timer  
• Low V detection and reset assertion  
CC  
—Five standard reset threshold voltages  
—Re-program low V reset threshold voltage  
CC  
using special programming sequence  
Applying power to the device activates the power-on  
reset circuit which holds RESET/RESET active for a  
period of time. This allows the power supply and oscilla-  
tor to stabilize before the processor can execute code.  
—Reset signal valid to V = 1V  
CC  
• Determine watchdog or low voltage reset with a  
volatile flag bit  
• Long battery life with low power consumption  
—<50µA max standby current, watchdog on  
—<1µA max standby current, watchdog off  
—<400µA max active current during read  
• 32Kbits of EEPROM  
The Watchdog Timer provides an independent protec-  
tion mechanism for microcontrollers. When the micro-  
controller fails to restart a timer within a selectable  
time out interval, the device activates the  
RESET/RESET signal. The user selects the interval  
from three preset values. Once selected, the interval  
does not change, even after cycling the power.  
• Built-in inadvertent write protection  
—Power-up/power-down protection circuitry  
—Protect 0, 1/4, 1/2 or all of EEPROM array with  
™
Block Lock protection  
The device’s low V  
detection circuitry protects the  
CC  
—In circuit programmable ROM mode  
• 2MHz SPI interface modes (0,0 & 1,1)  
• Minimize EEPROM programming time  
—32-byte page write mode  
user’s system from low voltage conditions, resetting the  
system when V falls below the minimum V trip  
CC  
CC  
point. RESET/RESET is asserted until V  
returns to  
CC  
proper operating level and stabilizes. Five industry stan-  
dard V thresholds are available, however, Intersil’s  
—Self-timed write cycle  
TRIP  
—5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V power supply  
operation  
unique circuits allow the threshold to be reprogrammed  
to meet custom requirements or to fine-tune the thresh-  
old for applications requiring higher precision.  
• Available packages  
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP  
• Pb-free plus anneal available (RoHS compliant)  
BLOCK DIAGRAM  
Watchdog Transition  
Detector  
Watchdog  
Timer Reset  
WP  
Protect Logic  
RESET/RESET  
X5323 = RESET  
SI  
Data  
Register  
Status  
Register  
SO  
Command  
Decode &  
Control  
Reset &  
Watchdog  
Timebase  
X5325 = RESET  
SCK  
8Kbits  
8Kbits  
CS/WDI  
Logic  
VCC Threshold  
Reset Logic  
16Kbits  
Power-on and  
Low Voltage  
Reset  
V
+
-
CC  
Generation  
V
TRIP  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
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