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X5325V14I-2.7 PDF预览

X5325V14I-2.7

更新时间： 2024-11-26 20:34:55
品牌 Logo 应用领域
瑞萨 - RENESAS 光电二极管
页数 文件大小 规格书
19页 826K
描述
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, PLASTIC, TSSOP-14

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中文翻译

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X5325V14I-2.7 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：PLASTIC, MO-153AC, TSSOP-14
针数：14Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.73Is Samacsys：N
可调阈值：YES模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：R-PDSO-G14长度：5 mm
信道数量：1功能数量：1
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：5 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

X5325V14I-2.7 数据手册

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DATASHEET  
X5323, X5325 (Replaces X25323, X25325)  
CPU Supervisor with 32kBit SPI EEPROM  
FN8131  
Rev 3.00  
December 9, 2015  
These devices combine four popular functions, Power-on  
Reset Control, Watchdog Timer, Supply Voltage Supervision,  
and Block Lock Protect Serial EEPROM Memory in one  
package. This combination lowers system cost, reduces  
board space requirements, and increases reliability.  
Features  
• Selectable watchdog timer  
• Low VCC detection and reset assertion  
- Five standard reset threshold voltages  
- Re-program low VCC reset threshold voltage using  
special programming sequence  
Applying power to the device activates the power-on reset  
circuit which holds RESET/RESET active for a period of  
time. This allows the power supply and oscillator to stabilize  
before the processor can execute code.  
- Reset signal valid to VCC = 1V  
• Determine watchdog or low voltage reset with a volatile  
flag bit  
The Watchdog Timer provides an independent protection  
mechanism for microcontrollers. When the microcontroller  
fails to restart a timer within a selectable time out interval,  
the device activates the RESET/RESET signal. The user  
selects the interval from three preset values. Once selected,  
the interval does not change, even after cycling the power.  
• Long battery life with low power consumption  
- <50µA max standby current, watchdog on  
- <1µA max standby current, watchdog off  
- <400µA max active current during read  
• 32kbits of EEPROM  
• Built-in inadvertent write protection  
- Power-up/power-down protection circuitry  
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block  
Lock™ protection  
The device’s low VCC detection circuitry protects the user’s  
system from low voltage conditions, resetting the system  
when VCC falls below the minimum VCC trip point.  
RESET/RESET is asserted until VCC returns to proper  
operating level and stabilizes. Five industry standard VTRIP  
thresholds are available, however, Intersil’s unique circuits  
allow the threshold to be reprogrammed to meet custom  
requirements or to fine-tune the threshold for applications  
requiring higher precision.  
- In circuit programmable ROM mode  
• 2MHz SPI interface modes (0,0 and 1,1)  
• Minimize EEPROM programming time  
- 32-byte page write mode  
- Self-timed write cycle  
- 5ms write cycle time (typical)  
• 2.7V to 5.5V and 4.5V to 5.5V power supply  
operation  
• Available packages  
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP  
• Pb-free (RoHS compliant)  
Block Diagram  
WATCHDOG TRANSITION  
DETECTOR  
WATCHDOG  
TIMER RESET  
WP  
PROTECT LOGIC  
RESET/RESET  
X5323 = RESET  
SI  
DATA  
REGISTER  
STATUS  
REGISTER  
SO  
RESET AND  
WATCHDOG  
TIMEBASE  
COMMAND  
DECODE AND  
CONTROL  
LOGIC  
X5325 = RESET  
SCK  
8kBITS  
8kBITS  
CS/WDI  
V
THRESHOLD  
RESET LOGIC  
CC  
16kBITS  
POWER-ON AND  
LOW VOLTAGE  
RESET  
V
+
-
CC  
GENERATION  
V
TRIP  
FN8131 Rev 3.00  
December 9, 2015  
Page 1 of 19  
1234567...19

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