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X28HC64DM-12 PDF预览

X28HC64DM-12

更新时间： 2024-11-23 22:15:55
品牌 Logo 应用领域
英特矽尔 - INTERSIL 内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
16页 309K
描述
5 Volt, Byte Alterable EEPROM

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X28HC64DM-12 数据手册

 浏览型号X28HC64DM-12的Datasheet PDF文件第2页浏览型号X28HC64DM-12的Datasheet PDF文件第3页浏览型号X28HC64DM-12的Datasheet PDF文件第4页浏览型号X28HC64DM-12的Datasheet PDF文件第5页浏览型号X28HC64DM-12的Datasheet PDF文件第6页浏览型号X28HC64DM-12的Datasheet PDF文件第7页 
X28HC64  
®
64K, 8K x 8 Bit  
Data Sheet  
June 1, 2005  
FN8109.0  
• High reliability  
—Endurance: 1 million cycles  
—Data retention: 100 years  
5 Volt, Byte Alterable EEPROM  
FEATURES  
• JEDEC approved byte-wide pin out  
• 70ns access time  
• Simple byte and page write  
—Single 5V supply  
—No external high voltages or V control circuits  
—Self-timed  
—No erase before write  
—No complex programming algorithms  
—No overerase problem  
• Low power CMOS  
DESCRIPTION  
The X28HC64 is an 8K x 8 EEPROM, fabricated with  
Intersil’s proprietary, high performance, floating gate  
CMOS technology. Like all Intersil programmable non-  
volatile memories, the X28HC64 is a 5V only device. It  
features the JEDEC approved pinto for byte-wide mem-  
ories, compatible with industry standard RAMs.  
PP  
—40mA active current max.  
—200µA standby current max.  
• Fast write cycle times  
—64-byte page write operation  
—Byte or page write cycle: 2ms typical  
—Complete memory rewrite: 0.25 sec. typical  
—Effective byte write cycle time: 32µs typical  
• Software data protection  
• End of write detection  
The X28HC64 supports a 64-byte page write operation,  
effectively providing a 32µs/byte write cycle, and  
enabling the entire memory to be typically written in 0.25  
seconds. The X28HC64 also features DATA Polling and  
Toggle Bit Polling, two methods providing early end of  
write detection. In addition, the X28HC64 includes a  
user-optional software data protection mode that further  
enhances Intersil’s hardware write protect capability.  
—DATA polling  
—Toggle bit  
Intersil EEPROMs are designed and tested for appli-  
cations requiring extended endurance. Inherent data  
retention is greater than 100 years.  
PIN CONFIGURATIONS  
TSOP  
LCC  
PLCC  
Plastic DIP  
A
A
A
I/O  
I/O  
I/O  
NC  
SS  
NC  
I/O  
I/O  
I/O  
A
A
A
A
A
A
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
Flat Pack  
CERDIP  
SOIC  
3
4
5
6
7
2
1
0
0
1
2
1
28  
27  
26  
25  
24  
23  
VCC  
NC  
A12  
A7  
4
3
2
1
32 31 30  
12  
2
NC  
NC  
V
WE  
NC  
A8  
V
A6  
A5  
A4  
A3  
A2  
A1  
A0  
5
29  
A8  
A9  
X28HC64  
3
CC  
6
7
28  
27  
NC  
WE  
NC  
4
A6  
3
4
5
6
7
A11  
NC  
OE  
A10  
22  
21  
5
A9  
A5  
8
9
26  
25  
A
A
9
A
I/O  
I/O  
20  
19  
18  
17  
8
6
A11  
A4  
X28HC64  
(Top View)  
7
X28HC64 22  
A3  
OE  
A10  
CE  
11  
10  
11  
24  
23  
A
OE  
10  
8
21  
20  
19  
18  
17  
16  
15  
A2  
CE  
9
A1  
CE  
I/O7  
I/O6  
12  
13  
22  
21  
NC  
10  
11  
12  
13  
14  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
A0  
I/O0  
PGA  
14 15 16 17 18 19 20  
I/O0  
I/O1  
I/O1  
12  
I/O2  
13  
I/O3  
15  
I/O5  
I/O4  
I/O6  
18  
17  
I/O2  
VSS  
I/O0  
11  
A0  
10  
VSS  
14  
I/O7  
19  
16  
A1  
A3  
A2  
8
CE  
20  
A10  
21  
9
7
5
X28HC64  
A4  
6
OE  
22  
A11  
23  
(BOTTOM  
VIEW)  
A5  
A6  
A12  
2
VCC  
28  
A9  
24  
A8  
25  
A7  
3
WE  
27  
NC  
26  
NC  
1
4
Bottom View  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2005. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
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