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X28HC64E-90

更新时间： 2024-02-07 18:47:26
品牌 Logo 应用领域
XICOR 内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
24页 114K
描述
5 Volt, Byte Alterable E2PROM

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中文翻译

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X28HC64E-90 数据手册

 浏览型号X28HC64E-90的Datasheet PDF文件第2页浏览型号X28HC64E-90的Datasheet PDF文件第3页浏览型号X28HC64E-90的Datasheet PDF文件第4页浏览型号X28HC64E-90的Datasheet PDF文件第5页浏览型号X28HC64E-90的Datasheet PDF文件第6页浏览型号X28HC64E-90的Datasheet PDF文件第7页 
64K  
X28HC64  
8K x 8 Bit  
5 Volt, Byte Alterable E2PROM  
FEATURES  
• High Reliability  
—Endurance: 100,000 Cycles  
• 55ns Access Time  
• Simple Byte and Page Write  
—Single 5V Supply  
—Data Retention: 100 Years  
• JEDEC Approved Byte-Wide Pinout  
—No External High Voltages or VPP Control  
Circuits  
—Self-Timed  
DESCRIPTION  
The X28HC64 is an 8K x 8 E2PROM, fabricated with  
Xicor’s proprietary, high performance, floating gate  
CMOS technology. Like all Xicor programmable non-  
volatilememoriestheX28HC64isa5Vonlydevice. The  
X28HC64featurestheJEDECapprovedpinoutforbyte-  
widememories,compatiblewithindustrystandardRAMs.  
—No Erase Before Write  
—No Complex Programming Algorithms  
—No Overerase Problem  
• Low Power CMOS  
—40 mA Active Current Max.  
—200 µA Standby Current Max.  
• Fast Write Cycle Times  
—64 Byte Page Write Operation  
—Byte or Page Write Cycle: 2ms Typical  
—Complete Memory Rewrite: 0.25 sec. Typical  
—Effective Byte Write Cycle Time: 32µs Typical  
• Software Data Protection  
• End of Write Detection  
The X28HC64 supports a 64-byte page write operation,  
effectively providing a 32µs/byte write cycle and en-  
abling the entire memory to be typically written in 0.25  
seconds. The X28HC64 also features DATA Polling and  
Toggle Bit Polling, two methods providing early end of  
write detection. In addition, the X28HC64 includes a  
user-optional software data protection mode that further  
enhances Xicor’s hardware write protect capability.  
—DATA Polling  
Xicor E2PROMs are designed and tested for applica-  
tions requiring extended endurance. Inherent data re-  
tention is greater than 100 years.  
—Toggle Bit  
TSOP  
PIN CONFIGURATIONS  
A
A
A
I/O  
I/O  
I/O  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A
A
A
A
A
A
NC  
NC  
V
NC  
WE  
NC  
A
A
A
2
1
0
0
1
2
3
4
5
6
7
12  
PLASTIC DIP  
LCC  
FLAT PACK  
PLCC  
NC  
CERDIP  
SOIC  
V
SS  
NC  
I/O  
I/O  
I/O  
I/O  
I/O  
X28HC64  
9
CC  
10  
11  
12  
13  
14  
15  
16  
3
4
5
6
7
NC  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
4
3
2
1
32 31 30  
29  
CC  
A
2
WE  
8
9
11  
12  
A
A
A
A
A
A
A
5
6
7
8
9
A
A
A
6
5
4
3
2
1
0
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
3
NC  
28  
27  
26  
25  
24  
23  
22  
21  
CE  
9
A
OE  
10  
4
A
8
A
9
11  
5
NC  
OE  
A
3857 ILL F22  
X28HC64  
PGA  
6
A
11  
10  
11  
12  
13  
7
OE  
10  
I/O  
12  
I/O  
13  
I/O  
15  
I/O  
17  
I/O  
18  
1
2
3
5
6
X28HC64  
CE  
8
A
10  
NC  
I/O  
I/O  
7
I/O  
11  
A
10  
V
14  
I/O  
16  
I/O  
19  
9
CE  
0
0
SS  
4
7
I/O  
0
6
10  
11  
12  
13  
14  
I/O  
7
I/O  
6
I/O  
5
I/0  
4
14 15 16 17 18 19 20  
A
A
A
8
CE  
20  
A
21  
1
3
2
4
10  
11  
I/O  
0
1
2
9
7
I/O  
I/O  
V
X28HC64  
A
6
OE  
22  
A
23  
3857 FHD F03  
I/O  
3
A
A
V
28  
A
24  
A
25  
SS  
5
6
12  
7
CC  
9
8
5
4
2
3
3857 FHD F02.1  
A
A
NC  
1
WE  
27  
NC  
26  
3857 FHD F04  
BOTTOM VIEW  
© Xicor, Inc. 1994, 1995, 1996 Patents Pending  
3857-3.0 8/5/97 T1/C0/D0 EW  
Characteristics subject to change without notice  
1
1234567...24

中文翻译

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