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W83194R-39 PDF预览

W83194R-39

更新时间: 2024-11-29 22:14:35
品牌 Logo 应用领域
华邦 - WINBOND 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
21页 272K
描述
100MHZ 3-DIMM CLOCK

W83194R-39 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP48,.4针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.77
Is Samacsys:N其他特性:ALSO REQUIRES 2.5V SUPPLY
JESD-30 代码:R-PDSO-G48JESD-609代码:e3
长度:15.88 mm端子数量:48
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:100.2 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
电源:2.5,3.3 V主时钟/晶体标称频率:14.318 MHz
认证状态:Not Qualified座面最大高度:2.79 mm
子类别:Clock Generators最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL宽度:7.49 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

W83194R-39 数据手册

 浏览型号W83194R-39的Datasheet PDF文件第2页浏览型号W83194R-39的Datasheet PDF文件第3页浏览型号W83194R-39的Datasheet PDF文件第4页浏览型号W83194R-39的Datasheet PDF文件第5页浏览型号W83194R-39的Datasheet PDF文件第6页浏览型号W83194R-39的Datasheet PDF文件第7页 
W83194R-39/-39A  
100MHZ 3-DIMM CLOCK  
1.0 GENERAL DESCRIPTION  
The W83194R-39/-39A is a Clock Synthesizer which provides all clocks required for high-speed RISC  
or CISC microprocessor such as Intel Pentium II. W83194R-39 provides eight different frequency of  
CPU and PCI clocks and W83194R-39A provides sixteen CPU/PCI frequencies which are externally  
selectable with smooth transitions. W83194R-39/-39A also provides 13 SDRAM clocks controlled by  
the none-delay buffer_in pin.  
The W83194R-39/-39A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V  
¡ Ó  
¡ Ó  
supply. Spread spectrum built in at 0.5% or 0.25% to reduce EMI. Programmable stopping  
individual clock outputs and frequency selection through I2C interface. The device meets the  
Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after  
power-up. It is not recommend to use the dual function pin for the slots(ISA, PCI, CPU, DIMM). The  
add on cards may have a pull up or pull down.  
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew  
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20  
¡ Ó  
pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48  
MHz provide better than 0.5V /ns slew rate.  
2.0 PRODUCT FEATURES  
·
·
·
·
·
·
Supports PentiumÔ II CPU with I2C.  
2 CPU clocks (one free-running CPU clock)  
13 SDRAM clocks for 3 DIMs  
6 PCI synchronous clocks  
One IOAPIC clock for multiprocessor support  
Optional single or mixed supply:  
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =  
3.3V, VddL1 = VdqL2 = 2.5V)  
·
·
·
·
·
·
< 250ps skew among CPU and SDRAM clocks  
< 250ps skew among PCI clocks  
< 5ns propagation delay SDRAM from buffer input  
Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.  
Smooth frequency switch with selections from 50 MHz to 133 MHz CPU  
I2C 2-Wire serial interface and I2C read back  
Publication Release Date: May 1998  
- 1 -  
Revision 0.20  

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