Datasheet > W83194R-67B

W83194R-67B

更新时间： 2024-02-16 18:58:24

品牌	Logo	应用领域
华邦 - WINBOND		时钟
页数	文件大小	规格书
18页	257K
描述
100MHZ 3-DIMM CLOCK FOR VIA MVP4

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技术参数
数据手册

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W83194R-67B 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP, SSOP48,.4	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.23
其他特性：	ALSO REQUIRES 2.5V SUPPLY	JESD-30 代码：	R-PDSO-G48
JESD-609代码：	e3	长度：	15.875 mm
端子数量：	48	最高工作温度：	70 °C
最低工作温度：		最大输出时钟频率：	133 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装等效代码：	SSOP48,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	电源：	2.5,3.3 V
主时钟/晶体标称频率：	14.318 MHz	认证状态：	Not Qualified
座面最大高度：	2.794 mm	子类别：	Clock Generators
最大供电电压：	3.465 V	最小供电电压：	3.135 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
宽度：	7.5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC

W83194R-67B 数据手册

W83194R-67B

100MHZ 3-DIMM CLOCK FOR VIA MVP4

1.0 GENERAL DESCRIPTION

The W83194R-67B is a Clock Synthesizer which provides all clocks required for high-speed RISC or

CISC microprocessor such as Intel Pentium , AMD and Cyrix. W83194R-67B provides sixteen

CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67B also

provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.

The W83194R-67B accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.

Spread spectrum built in at ±0.5% or ±0.25% to reduce EMI. Programmable stopping individual

clock outputs and frequency selection through I²C interface. The device meets the Pentium power-up

stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up.

High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew

rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20

pF loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48

MHz provide better than 0.5V /ns slew rate.

2.0 PRODUCT FEATURES

Supports Pentium , AMD, Cyrix CPU with I²C.

4 CPU clocks (one free-running CPU clock)

13 SDRAM clocks for 3 DIMs

6 PCI synchronous clocks

Optional single or mixed supply:

(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =

3.3V, VddL1 = VdqL2 = 2.5V)

< 250ps skew among CPU and SDRAM clocks

< 4ns propagation delay SDRAM from buffer input

Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.

Smooth frequency switch with selections from 60 MHz to 124 MHz CPU

I²C 2-Wire serial interface and I²C read back

0~0.5% down type or ±0.25% or ±0.5% spread spectrum function to reduce EMI

Programmable registers to enable/stop each output and select modes

(mode as Tri-state or Normal )

2ms power up clock stable time

MODE pin for power Management

One 48 MHz for USB & one 24 MHz for super I/O

Packaged in 48-pin SSOP

Publication Release Date: Dec. 1999

- 1 -

Revision 0.50

12 3 4 5 6 7...18

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